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LTM4633 Arkusz danych(PDF) 14 Page - Linear Technology

Numer części LTM4633
Szczegółowy opis  Triple 10A Step-DownDC/DC 關Module Regulator
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Producent  LINER [Linear Technology]
Strona internetowa  http://www.linear.com
Logo LINER - Linear Technology

LTM4633 Arkusz danych(HTML) 14 Page - Linear Technology

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LTM4633
14
4633f
For more information www.linear.com/LTM4633
applicaTions inForMaTion
VTRACK is the track ramp applied to the slave’s track pin.
VTRACK has a control range of 0V to 0.8V, or the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when VTRACK is more than 0.8V. RTA in
Figure 2 will be equal to the RFB2 for coincident tracking.
The TK/SS pin of the master can be controlled by a capaci-
tor placed on the master regulator TK/SS pin to ground. A
1.5µA current source will charge the TK/SS pin up to the
reference voltage and then proceed up to INTVCC. After the
0.8V ramp, the TK/SS pin will no longer be in control, and
the internal voltage reference will control output regula-
tion from the feedback divider. Foldback current limit is
disabled during this sequence of turn-on during tracking
or soft-starting. The TK/SS pins are pulled low when the
RUN pin is below 1.3V or INTVCC drops below 3.5V. The
total soft-start time can be calculated as:
tSS =
0.8V •CSS
1.5µA


Regardless of the mode selected by the MODE/PLLIN pin,
the regulator channels will always start in pulse-skipping
mode up to TK/SS = 0.64V. Between TK/SS = 0.64V and
0.74V, it will operate in forced continuous mode and revert
totheselectedmodeonceTK/SS>0.74V.Theoutputripple
is minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the ramp
rate of the other supply’s voltage. Note that the small soft-
RFB3
19.1k
RFB2
121k
RFB1
69.8k
COUT3
470µF
COUT6
470µF
COUT8
100µF
COUT2
100µF
220pF
1.5V
VFB1
VFB1
VFB2
1.2V
3.3V
COUT5
100µF
220pF
VFB3
100pF
COUT1
100µF
CSS3
0.1µF
VOUT3
VOUT3
RTA
121k
SOFT-START MASTER
RAMP SET BY CSS1 OR
EXTERNAL RAMP
UVLO SET AT 6V ON RUN PINS.
RUN PINS CAN BE SEQUENCED OR
ENABLED FROM LOGIC CONTROL
MASTER
OUTPUT RAMP
FED TO SLAVE
COUT, SEE TABLE 5
RTB 60.4k
13.3k
60.4k
69.8k
CIN1
22µF
16V
CIN2
22µF
16V
CIN3
22µF
16V
CIN4
22µF
16V
COUT4
100µF
COUT7
100µF
10k
10k
CNTL_PWR
MODE/PLLIN
RUN1
RUN2
RUN3
TK/SS2
TK/SS3
FREQ/PLLLPF
COMP1
COMP2
COMP3
PGOOD12
PGOOD3
TEMP1
TEMP2
VOUT1 VFB1
VOUT2 VFB2
VOUT3 VFB3
4633 F02
GND SGND
VIN1 SW1
VIN2
4.7V TO 16V
SW2
VIN3
LTM4633
SW3
4.7µF
6.3V
INTVCC EXTVCC
TK/SS1
VFB2
VFB3
Figure 2. Triple Outputs, 1.5V and 1.2V Tracking to 3.3V


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