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AK4376A Arkusz danych(PDF) 40 Page - Asahi Kasei Microsystems |
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AK4376A Arkusz danych(HTML) 40 Page - Asahi Kasei Microsystems |
40 / 68 page [AK4376A] 016014206-E-00 2016/11 - 40 - Table 19. VDD Mode Holding Period Setting (x: Do not care) VDDTM[3:0] bits VDD Mode Holding Period 8 kHz 44.1 kHz 96 kHz 192 kHz 0000 1024/fs 128 ms 23.2 ms 10.7 ms 5.3 ms (default) 0001 2048/fs 256 ms 46.4 ms 21.3 ms 10.7 ms 0010 4096/fs 512 ms 92.9 ms 42.7 ms 21.3 ms 0011 8192/fs 1024 ms 186 ms 85.3 ms 42.7 ms 0100 16384/fs 2048 ms 372 ms 170.7 ms 85.3 ms 0101 32768/fs 4096 ms 743 ms 341.3 ms 170.7 ms 0110 65536/fs 8192 ms 1486 ms 682.7 ms 341.3 ms 0111 131072/fs 16384 ms 2972 ms 1365.3 ms 682.7 ms 1xxx 262144/fs 32768 ms 5944 ms 2730.7 ms 1365.3 ms Note 71. Oct speed mode (fs = 256 k / 352.8 k / 384 kHz) has the same cycle as fs = 32 k / 44.1 k / 48 kHz. When the output voltage becomes less than class-G mode switching level, the internal detection counter for 1/2 VDD mode which is set by LVDTM[2:0] bits starts. This counter is reset when the output voltage exceeds class-G mode switching level. The charge pump operation mode is changed to VDD from 1/2 VDD if the detection counter of 1/2VDD mode is finished and also the VDD mode hold period is passed. Detection Time (LVTDM[2:0]bits) VDD Under 1/2 VDD Level 1/2VDD VDD(Start) 1) Detection Time < 1/2 VDD Level VDD 2) Detection Time > 1/2 VDD Level Class-G Mode Class-G Mode Class-G Mode Switching Level Class-G Mode Switching Level Figure 16. Transition to 1/2 VDD Mode from VDD Mode |
Podobny numer części - AK4376A |
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Podobny opis - AK4376A |
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