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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AK4376A Arkusz danych(PDF) 55 Page - Asahi Kasei Microsystems |
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AK4376A Arkusz danych(HTML) 55 Page - Asahi Kasei Microsystems |
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55 / 68 page  [AK4376A] 016014206-E-00 2016/11 - 55 - <Sequence> (1) Set the PDN pin “L” → “H” after the AK4376A is powered up. In this case, 1ms or more “L” time is needed for a certain reset. (MCKI, BCLK, LRCK, SDATA, SCL and SDA should be input after all power supplies are ON.) (2) Set the PDN pin = “H” to release the power down. Register access will be valid after 0.8 ms. However, a wait time of 10 ms is needed to access power management bits of the analog circuit (PMCP1 bit, PMCP2 bit, PMLDO1P bit, PMLDO1N bit, PMDAC bit, PMHPL bit, PMHPR bit, PMPLL bit) until the analog circuit is powered up. Execute register write after analog circuit is powered up. (3) Input MCKI, BCLK and LRCK. (4) Set sampling frequency (FS[4:0] bits) and the input signal path of the DAC (LDACL bit = RDACR bit = “0” → “1”). (5) Set DAC digital volume by OVL[4:0] bits. Both Lch and Rch volumes are controlled by OVL[4:0] bits when OVOLCN bit = “1” (default). (6) Power up CP1 (PMCP1 bit= “0” → “1”) LDO1P and LDO1N should be powered up (PMLDO1P bit = PMLDO1N bit = "0"→"1") after 6.5 ms (Note 75) from CP1 power-up. (7) Power up DAC (PMDA bit = “0” → “1”) DAC must be powered up after 1 ms (Note 75) from LDO1P and LDO2P power up. (8) Power up CP2 (PMCP2 bit = “0” → “1”) CP2 must be powered up after LDO1P and LDO1N are powered up. (9) Power up HPL and HPR (PMHPL bit = PMHPR bit = “0” → “1”) HPL and HPR should be powered up after 4.5 ms (Note 75) from CP2 power up. The power-up time of HP-Amp is 25.9 ms (@ fs = 44.1 kHz). The HPL pin and the HPR pin output 0 V until the HP-Amp is powered up. Note 75. Refer to “■ Charge Pump & LDO Circuit Power-up Time” |
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Podobny opis - AK4376A |
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