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AK5522 Arkusz danych(PDF) 74 Page - Asahi Kasei Microsystems

Numer części AK5522
Szczegółowy opis  Differential Input Stereo 32-bit ADC with Excellent PSRR
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Producent  AKM [Asahi Kasei Microsystems]
Strona internetowa  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK5522 Arkusz danych(HTML) 74 Page - Asahi Kasei Microsystems

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[AK5522]
017002311-E-00
2017/03
- 74 -
READ Operations
Set the R/W bit = “1” for the READ operation of the AK5522. After transmission of data, the master can
read the next address’s data by generating acknowledge instead of terminating the write cycle after the
receipt of the first data word. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “04H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK5522 supports two basic read operations: Current Address Read and Random Address Read.
(1) Current Address Read
The AK5522 contains an internal address counter that maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either a read or write) was to address “n”, the next
CURRENT READ operation would access data
from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK5522 generates acknowledge, transmits 1-byte of data to the address set by the
internal address counter and increments the internal address counter by 1. If the master does not
generate acknowledge but generates a stop condition instead, the AK5522 ceases transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n+1)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
A
C
K
R/W=
“1”
A
C
K
Data(n)
Figure 76. Current Address Read
(2) Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
a slave address with the R/W bit =“1”, the master must execute a “dummy” write operation first. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit =“1”. The AK5522 then generates acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate acknowledge but generates a stop
condition instead, the AK5522 ceases transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W=
“0”
A
C
K
Sub
Address(n)
S
T
A
R
T
A
C
K
S
Slave
Address
R/W=
“1”
Figure 77. Random Address Read


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