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LM2501SL Arkusz danych(PDF) 10 Page - National Semiconductor (TI) |
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LM2501SL Arkusz danych(HTML) 10 Page - National Semiconductor (TI) |
10 / 14 page Functional Description (Continued) In Figure 6, the Serializer timing is shown. For the part to establish lock, WCLKIO(out) must be active, and a valid PCLK applied. After lock is obtained, the MC and MD lines are initialized and then active transmission occurs. Table Switching Characteristics lists the timing parameters of Fig- ures 5, 6. SERIAL BUS POWER-OFF In the power-off state, WC, MD and MC are turned off with zero current flowing. This is considered the Sleep state (Power-off) and the transition off may occur after the last data bit time or at any time afterwards from an Idle phase as shown in Figure 7. 20091604 FIGURE 6. Bus Power Up Timing — MC/MD 20091605 FIGURE 7. Bus Power Down Timing www.national.com 10 |
Podobny numer części - LM2501SL |
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Podobny opis - LM2501SL |
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