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FPV1006-150-R Arkusz danych(PDF) 5 Page - Vicor Corporation

Numer części FPV1006-150-R
Szczegółowy opis  8V to 36VIN Cool-Power ZVS Buck Regulator Family
Download  41 Pages
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Producent  VICOR [Vicor Corporation]
Strona internetowa  http://www.vicorpower.com
Logo VICOR - Vicor Corporation

FPV1006-150-R Arkusz danych(HTML) 5 Page - Vicor Corporation

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Cool-Power® ZVS Switching Regulators
Rev 2.5
Page 5 of 41
06/2017
PI33xx-x0
Package Pin-Out
Pin Description
PWRGD
VS1
Block 4
VIN
Block 3
PGND
Block 2
SGND
ADJ
TRK
SDA
SCL
ADR0
ADR1
K
J
H
G
F
E
D
C
B
A
13
12
5
4
3
1
14
210
9
8
7
611
SGND
Block 1
VOUT
Block 5
Block 1:
B2-4, C2-4, D2-3, E2-3, F1-3, G2-3, H2-3, J1-3, K1-2
Block 2:
A8-10, B8-10, C8-10, D8-10, E4-10,
F4-10, G4-10, H4-10, J4-10, K6-10
Block 3:
G12-14, H12-14, J12-14, K12-14
Block 4:
A12-14, B12-14, C12-14, D12-14, E12-14
Block 5:
A6-7, B6-7, C6-7, D6-7
Pin Name
Number
Description
SGND
Block 1
Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO, ADJ and I2C (options) communication returns. SGND
and PGND are star connected within the regulator package.
PGND
Block 2
Power Ground: VIN and VOUT power returns.
VIN
Block 3
Input Voltage: and sense for UVLO, OVLO and feed forward ramp.
VOUT
Block 5
Output Voltage: and sense for power switches and feed-forward ramp.
VS1
Block 4
Switching Node: and ZVS sense for power switches.
PWRGD
A1
Power Good: High impedance when regulator is operating and VOUT is in regulation.
Otherwise pulls to SGND. Also can be used for parallel timing management intended for lead regulator.
EAO
A2
Error Amp Output: External connection for additional compensation and current sharing.
EN
A3
Enable Input: Regulator enable control. Asserted high or left floating – regulator enabled;
Asserted low, regulator output disabled. Polarity is programmable via I2C interface.
REM
A5
Remote Sense: High side connection. Connect to output regulation point.
ADJ
B1
Adjust Input: An external resistor may be connected between ADJ pin and SGND or VOUT
to trim the output voltage up or down.
TRK
C1
Soft-start and Track Input: An external capacitor may be connected between TRK pin
and SGND to decrease the rate of rise during soft-start.
NC
A4
No Connect: Leave pins floating.
VDR
K3
VDR can only be used for ADR0 and ADR1 pull up reference voltage.
No other external loading is permitted
SYNCO
K4
Synchronization Output: Outputs a low signal for ½ of the minimum period for synchronization of other converters.
SYNCI
K5
Synchronization Input: Synchronize to the falling edge of external clock frequency.
SYNCI is a high impedance digital input node and should always be connected to SGND when not in use.
SDA
D1
Data Line: Connect to SGND for PI33xx-00. For use with PI33xx-20 only.
SCL
E1
Clock Line: Connect to SGND for PI33xx-00. For use with PI33xx-20 only.
ADR1
H1
Tri-state Address: No connect for PI33xx-00. For use with PI33xx-20 only.
ADR0
G1
Tri-state Address: No connect for PI33xx-00. For use with PI33xx-20 only.


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