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ADM1033ARQZ-REEL Arkusz danych(PDF) 5 Page - Analog Devices |
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ADM1033ARQZ-REEL Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 40 page ADM1033 Rev. 0 | Page 5 of 40 Parameter Min Typ Max Units Test Conditions/Comments TACHOMETER ACCURACY Fan Speed Measurement Accuracy ±4 % AGTL + INPUT (THERM) Input High Level 0.75 × REF V Input Low Level 0.4 V SERIAL BUS TIMING3 See Figure 2 Clock Frequency, fSCLK 400 kHz Glitch Immunity, tSW 50 ns Bus Free Time, tBUF 1.3 µs Start Setup Time, tSU:STA 0.6 µs Start Hold Time, tHD:STA 0.6 µs Stop Condition Setup Time, tSU:STO 0.6 µs SCL Low Time, tLOW 1.3 µs SCL High Time, tHIGH 0.6 µs SCL, SDA Rise Time, tr 1000 ns SCL, SDA Fall Time, tf 300 ns Data Setup Time, tSU:DAT 100 ns Detect Clock Low Timeout, tTIMEOUT 25 35 ms See Note 4 1 Typicals are at TA = 25°C and represent most likely parametric norm. Standby current typ is measured with VCC = 3.3 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge. 2 Operation at 5.5 V is guaranteed by design, not production tested. 3 Guaranteed by design, not production tested. 4 SMBus timeout disabled by default. See the SMBus Timeout section for more information. P S tLOW tR tF tHD:STA tHD:DAT tSU:DAT tSU:STA tHD:STA tSU:STO tHIGH SCL PS SDA tBUF Figure 2. Serial Bus Timing Diagram |
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