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FIN24AGFX Arkusz danych(PDF) 3 Page - Fairchild Semiconductor |
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FIN24AGFX Arkusz danych(HTML) 3 Page - Fairchild Semiconductor |
3 / 20 page Preliminary 3 www.fairchildsemi.com Terminal Description Note 1: The DSO/DSI serial port pins have been arranged such that when one device is rotated 180 degrees with respect to the other device the serial con- nections will properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. Control Logic Circuitry The FIN24A has the ability to be used as a 24-bit Serializer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. The table below shows the pin programming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device will be configured as a serializer. Chang- ing the state on the DIRI signal will reverse the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bi-directional operation the DIRI of the master device will be driven by the system and the DIRO signal of the master will be used to drive the DIRI of the slave device. Serializer/Deserializer with Dedicated I/O Variation The serialization and deserialization circuitry is setup for 24 bits. Because of the dedicated inputs and outputs only 22 bits of data are ever serialized or deserialized. Regardless of the mode of operation the serializer is always sending 24 bits of data plus 2 boundary bits and the deserializer is always receiving 24 bits of data and 2 word boundary bits. Bits 23 and 24 of the serializer will always contain the value of zero and will be discarded by the deserializer. DP[21:22] input to the serializer will be deserialized to DP[23:24] respectively. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH Impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer the dedicated outputs will remain at the last logical value asserted. This value will only change if the device is once again turned around into a deserializer and the values are overwritten. Terminal Name I/O Type Number of Terminals Description of Signals DP[1:20] I/O 20 LVCMOS Parallel I/O. Direction controlled by DIRI pin DP[21:22] I 2 LVCMOS Parallel Unidirectional Inputs DP[23:24] O 2 LVCMOS Unidirectional Parallel Outputs CKREF IN 1 LVCMOS Clock Input and PLL Reference STROBE IN 1 LVCMOS Strobe Signal for Latching Data into the Serializer CKP OUT 1 LVCMOS Word Clock Output DSO / DSI DSO / DSI DIFF-I/O 2 LpLVDS Differential Serial I/O Data Signals (Note 1) DSO: Refers to output signal pair DSI: Refers to input signal pair DSO(I) : Positive signal of DSO(I) pair DSO(I) : Negative signal of DSO(I) pair CKSI , SKSI DIFF-IN 2 LpLVDS Differential Deserializer Input Bit Clock CKSI: Refers to signal pair CKSI : Positive signal of CKSI pair CKSI : Negative signal of CKSI pair CKSO , SKSO DIFF-OUT 2 LpLVDS Differential Serializer Output Bit Clock CKSO: Refers to signal pair CKSO : Positive signal of CKSO pair CKSO : Negative signal of CKSO pair S1 IN 1 LVCMOS Mode Selection terminals used to select S2 IN 1 Frequency Range for the RefClock, CKREF DIRI IN 1 LVCMOS Control Input Used to control direction of Data Flow: DIRI “1” Serializer, DIRI “0” Deserializer DIRO OUT 1 LVCMOS Control Output Inversion of DIRI VDDP Supply 1 Power Supply for Parallel I/O and Translation Circuitry VDDS Supply 1 Power Supply for Core and Serial I/O VDDA Supply 1 Power Supply for Analog PLL Circuitry GND Supply 0 Use Bottom Ground Plane for Ground Signals |
Podobny numer części - FIN24AGFX |
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Podobny opis - FIN24AGFX |
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