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AD805BN Arkusz danych(PDF) 4 Page - Analog Devices |
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AD805BN Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 12 page AD805 –4– REV. 0 GLOSSARY AD805 performance is specified using a Vectron C0-434Y ECL Series Hybrid VCXO, SCD No. 434Y2365. Nominal Data Rate This is the data rate that the circuit is specified to operate on. The data format is Nonreturn to Zero (NRZ). Operating Temperature Range (TMIN to TMAX) This is the operating temperature range of the AD805 in the circuit. Each of the additional components of the circuit is held at 25 °C, nominal. The operating temperature range of the circuit can be extended to the operating temperature range of the AD805 through the selection of circuit components that operate from TMIN to TMAX. Tracking Range This is the range of input data rates over which the circuit will remain in lock. The VCXO CONTROL voltage range and the VCXO frequency range determine circuit tracking range. Capture Range This is the range of frequencies over which the circuit can acquire lock. The VCXO CONTROL voltage range and the VCXO frequency range determine circuit capture range. Static Phase Error This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error and IC input and output signals prohibit direct measurement of static phase error. Recovered Clock Skew, TRCS This is the time difference, in ns, between the recovered clock signal rising edge midpoint and midpoint of the rising or falling edge of the output data signal. Refer to Figure 1. Data Transition Density, This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. ρ is the ratio (0 ≤ ρ ≤ 1) of data transitions to clock periods. Transitionless Data Run This is measured by interrupting an input data pattern with ρ = 1/2 with a block of data bits without transitions, and then reapplying the ρ = 1/2 input data. The circuit will handle this sequence without making a bit error. The length of the block of input data without transitions that an AD805-VCXO circuit can handle is a function of the VCXO K0. The VCXO in the circuit of Figure 12 has a K0 of 60 radians/volt, nominally. Jitter This is the dynamic displacement of digital signals from their long term average positions, measured in degrees rms, or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock. Jitter on the recovered clock causes jitter on the retimed data. Output Jitter This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudo-random input data sequence (PRN Sequence). The random output jitter of the VCXO contributes to Output Jitter. Jitter Tolerance Jitter tolerance is a measure of the circuit’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation and is usually specified in Unit Intervals (UI). The circuit will have a bit error rate less than 1 × 10–10 when in lock and retiming input data that has the specified jitter applied to it. Refer to the THEORY OF OPERATION section for a descrip- tion of the jitter tolerance of the AD805-VCXO circuit. Jitter Transfer The circuit exhibits a low-pass filter response to jitter applied to its input data. The circuit jitter transfer characteristics are measured using the method described in CCITT Recommenda- tion G.958, Geneva 1990, Section 6.3.2. This method involves applying sinusoidal input jitter up to the jitter tolerance mask level for an STM-1 Type A regenerator. Bandwidth This describes the frequency at which the circuit attenuates sinusoidal input jitter by 3 dB. Peaking This describes the maximum jitter gain of the circuit in dB. Acquisition Time This is the transient time, measured in bit periods, required for the circuit to lock on input data from its free-running state. Buffered Clock Distortion This is a measure of the duty cycle distortion at the AD805 CLKOUT signals relative to the duty cycle distortion at the AD805 CLKIN signals. Bit Error Rate vs. Signal-to-Noise Ratio The AD805 is intended to operate with standard ECL signal levels at the data input. Although not recommended, smaller input signals are tolerable. Figure 6 shows the bit error rate performance versus input signal-to-noise ratio for input signal amplitudes of full 900 mV ECL, and decreased amplitudes of 80 mV and 20 mV. Wideband amplitude noise is summed with the data signals as shown in Figure 2. The full ECL, 80 mV, and 20 mV input signals give virtually indistinguishable results. The axes used for Figure 6 are scaled so that the theoretical Bit Error Rate vs. Signal to Noise Ratio curve appears as a straight line. The curve that fits the actual data points has a slope that matches the slope of the theoretical curve for all but the higher values of signal-to-noise ratio and lower values of bit error rate. For high values of signal-to-noise ratio, the noise generator used clips, and therefore is not true Gaussian. The extreme peaks of the noise cause bit errors for high signal to noise ratios and low bit error rates. The clipping of the noise waveform limits bit errors in these cases. OBSOLETE |
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