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CDCM1802RGTR Arkusz danych(PDF) 3 Page - Texas Instruments |
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CDCM1802RGTR Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 22 page CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION EN 16 I (with 60-kΩ pullup) ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three different configurations: tie to GND (logic 0), external 60-kΩ pulldown resistor (pull to VDD/2) or left floating (logic 1); EN = 1: outputs on according to S0 and S1 setting EN = VDD/2: outputs on according to S0 and S1 setting EN = 0; outputs Y[1:0] off (high-impedance) see Table 1 for details. IN IN 2 3 I Differential input Differential input clock. Input stage is sensitive and has a wide common mode range. Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML, HSTL). Since the input is high-impedance, it is recommended to terminate the PCB transmission line before the input (e.g. with 100-Ω across input). The input can also be driven by a single-ended signal, if the complementary input is tied to a dc reference voltage (e.g. VCC/2). The inputs deploy an ESD structure protecting the inputs in case of an input voltage exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through this inputs is possible and must be prevented by limiting the input voltage < VDD S0 S1 13 15 I I (with 60-kΩ pullup) Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers three different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull to VDD/2) or left floating (logic 1); see Table 1 for details Y1 7 O LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock IN based on the selected mode of operation: S0, S1, and EN. Also, this output can be disabled by tying VDD1 to GND. Y0 Y0 10 11 O LVPECL LVPECL clock output. This output provides a copy of IN or a divided down copy of clock IN based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the output can simply be left open to save power and minimize noise impact to Y1. VBB 4 O Output bias voltage used to bias unused complementary input IN for single-ended input signals. The output voltage of VBB is VDD −1.3 V. When driving a load, the output current drive is limited to about 1.5 mA. VSS 5, 6, 14 Supply Device ground VDDPECL 1 Supply Supply voltage PECL input + internal logic VDD0 9, 12 Supply PECL output supply voltage for output Y0; Y0 can be disabled by pulling VDD0 to GND. Caution: In this mode no voltage from outside may be forced because internal diodes could be forced in a forward direction. Thus, it is recommended to leave the output disconnect VDD1 8 Supply Supply voltage CMOS output; The CMOS output can be disabled by pulling VDD1 to GND. Caution: In this mode no voltage from outside may be forced, because internal diodes could be forced in forward direction. Thus, it is recommended to leave Y1 unconnected, tied to GND or terminated into GND |
Podobny numer części - CDCM1802RGTR |
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Podobny opis - CDCM1802RGTR |
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