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CDCM7005RGZR Arkusz danych(PDF) 4 Page - Texas Instruments

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Numer części CDCM7005RGZR
Szczegółowy opis  3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
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Strona internetowa  http://www.ti.com
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CDCM7005
SCAS793A – JUNE 2005 – REVISED JUNE 2005
Table 1. PIN ASSINGMENT
TERMINAL
I/O
DESCRIPTION
NAME
BGA
QFN
D7, E3,
2, 5, 6,
E4, E5,
9, 10,
E6, E7,
13, 15,
3.3-V supply. There is no internal connection between VCC and AVCC. It is
VCC
E8, F7,
18, 19,
Power
recommended that AVCC use its own supply filter.
G2, G3,
20, 21,
G4, G5,
41, 44,
G6, G7
45; 48
B2, B3,
B4, B5,
B6, B7,
B8, C2,
Thermal
D2, D3,
GND
pad and
Ground
Ground
D4, D5,
pin 24
D6, E2,
F2, F3,
F4, F5,
F6
C3, C4,
27, 30,
Analog
3.3-V analog power supply. There is no internal connection between AVCC and
AVCC
C5, C6,
32, 38,
Power
VCC. It is recommended that AVCC use its own supply filter.
C7
39
This is the charge pump power supply pin used to have the same supply as the
VCC_CP
A3
33
Power
external VCO. It can be set from 2.3 V to 3.6 V.
LVCMOS input, control latch enable for serial programmable Interface (SPI), with
CTRL_LE
A5
29
I
hysteresis
CTRL_CLK
A6
28
I
LVCMOS input, serial control clock input for SPI, with hysteresis
CTRL_DATA
A7
26
I
LVCMOS input, serial control data input for SPI, with hysteresis
LVCMOS input, asynchronous power down (PD) signal. This pin is low active and
can be activated external or by the corresponding bit in the SPI register (in case of
logic high, the SPI setting is valid). Switches the device into power-down mode.
PD
H1
1
I
Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or
PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin
and all Yx outputs. Sets the SPI register to default value; has internal 150-k
pullup resistor.
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
RESET or
is not edge triggered and should have a pulse duration of at least 5 ns.
H8
14
I
HOLD
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.
The input has an internal 150-k
Ω pullup resistor.
VCXO_IN
E1
43
I
VCXO LVPECL input
VCXO_IN
D1
42
I
Complementary VCXO LVPECL input
LVCMOS input for the primary reference clock, with an internal 150-k
Ω pullup
PRI_REF
A1
36
I
resistor and input hysteresis.
LVCMOS input for the secondary reference clock, with an internal 150-k
Ω pullup
SEC_REF
B1
37
I
resistor and input hysteresis.
LVCMOS reference clock selection input. In the manual mode the REF_SEL
signal selects one of the two input clocks:
REF_SEL
A2
35
I
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-k
Ω pullup resistor.
CP_OUT
A4
31
O
Charge pump output
4


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