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TEA2029C Arkusz danych(PDF) 3 Page - STMicroelectronics |
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TEA2029C Arkusz danych(HTML) 3 Page - STMicroelectronics |
3 / 9 page GENERAL DESCRIPTION This integrated circuit uses I 2L bipolar technology and combines analog signal processing with digital processing. Timing signals are obtained from a voltage-control- led oscillator (VCO) operatingat 500KHz by means of a cheap ceramic resonator. This avoids the frequency adjustment normally required with line and frame oscillators. A chain of dividers and appropriate logic circuitry produce very accurately defined sampling pulses and the necessary timing signals. The principal functions implemented are : - Horizontal scanning processor. - Frame scanning processor. Two applications are possible : - D Class : Po wer stage using an external thyristor. - B Class : Power stage using an external power amplifier with fly-back generator such as the TDA8170. - Secondary switch mode power regulation. The SMPS output synchronize a primary I.C. (TEA2260/61) at the mains part. This concept allows ACTIVE STANDBY facilities. - Dual phase-locked loop horizontal scanning. - High performance frame and line synchronization with interlacing control. - Video identification circuit. - Super sandcastle. - AGC key pulse output. - Automatic 50-60Hz standard identification. - VCR input for PLL time constant and frame syn- chro switching. - Frame saw-tooth generator and phase modula- tor. - Switching mode regulated power supply compris- ing error amplifier and phase modulator. - Security circuit and start-up processor. - 500kHz VCO The circuit is supplied in a 28 pin DIP case. VCC = 12V. Synchronization Separator Line synchronization separator is clamped to black level of input video signal with synchroniza- tion pulse bottom level measurement. The synchronization pulses are divided centrally between the black level and the synchronization pulse bottom level, to improve performance on video signals in noise conditions. Frame Synchronization Frame synchronization is fully integrated (no ex- ternal capacitor required). The frame timing identification logic permits auto- matic adaptation to 50 - 60Hz standards or non-in- terlaced video. An automatic synchronization window width sys- tem provides : - fast frame capture (6.7ms wide window), - good noise immunity (0.4ms narrow window). The internal generator starts the discharge of the saw-tooth generator capacitor so that it is not dis- turbed by line fly back effects. Thanks to the logic control, the beginning of the charge phase does not depend on any disturbing effect of the line fly-back. A32 µs timing is automatically applied on stan- dardized transmissions, for perfect interlacing. In VCR mode, the discharge time is controlled by an internal monostable independent of the line frequency and gives a direct frame synchroniza- tion. Horizontal Scanning The horizontalscanning frequency is obtainedfrom the 500kHz VCO. The circuit uses two phase-locked loops (PLL) : the first one controls the frequency, the second one controls the relative phase of the synchronization and line fly-back signals. The frequency PLL has two switched time con- stants to provide : - capture with a short time constant, - good noise immunity after capture with a long time constant. The output pulse has a constant duration of 26 µs, independent of VCC and any delay in switching off the scanning transistor. Video Identification The horizontal synchronization signal is sampled by a 2 µs pulse within the synchronization pulse. The signal is integrated by an external capacitor. The identification function provides three different levels : - 0V : no video identification - 6V : 60Hz video identification - 12V : 50Hz video identification This information may be used for timing research in the case of frequency or voltage synthetizer type receivers, and for audio muting. Super Sandcastle with 3 levels : burst, line fly- back, frame blanking In the event of vertical scanning failure, the frame blanking level goes high to protect the tube. Frame blanking time (start with reset of Frame divider) is 24 lines. VCR Input This provides for continuous use of the short time constant of the first phase-locked loop (frequency). In VCR mode, the frame synchronization window TEA2029C 3/9 |
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