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SM89516Q Arkusz danych(PDF) 7 Page - SyncMOS Technologies,Inc |
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SM89516Q Arkusz danych(HTML) 7 Page - SyncMOS Technologies,Inc |
7 / 19 page May 2001 Specifications subject to change without notice,contact your sales representatives for the most recent information. 7/19 Ver 1.3 PID 89516 05/01 SyncMOS Technologies Inc. SM89516 Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 * * * * 1 1 1 1 Reset value MSB LSB port4 (P4, $D8) The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively. Port 4 for PLCC or QFP package: The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3. Extension Function Description Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. The SM89516 WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly. The WDT is enable by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM89516 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning. SM89516 has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0). RAMS1 RAMS0 MOVX @Ri i=0,1 mapping to expended RAM address 0 0 $0000 ~ $00FF 0 1 $0100 ~ $01FF 1 0 $0200 ~ $02FF |
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