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AD1839A Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD1839A
Szczegółowy opis  2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD1839A Arkusz danych(HTML) 6 Page - Analog Devices

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AD1839A
Rev. B | Page 6 of 24
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
BCLK Delay
40
ns
From MCLK rising edge
tFSD
FSTDM Delay
5
ns
From BCLK rising edge
tTABDD
ASDATA Delay
10
ns
From BCLK rising edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK falling edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK falling edge
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
256 × fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK falling edge
tTFH
FSTDM Hold
10
ns
From BCLK falling edge
tTBDD
ASDATA Delay
15
ns
From BCLK rising edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK falling edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK falling edge
TDM512 MODE (Master, 48 kHz)
tTBD
BCLK Delay
40
ns
From MCLK rising edge
tFSD
FSTDM Delay
5
ns
From BCLK rising edge
tTABDD
ASDATA Delay
10
ns
From BCLK rising edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK falling edge
tTDDH
DSDATA1 Hold
15
ns
From BCLK falling edge
TDM512 MODE (Slave, 48 kHz)
fAB
BCLK Frequency
512 × fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK falling edge
tTFH
FSTDM Hold
10
ns
From BCLK falling edge
tTBDD
ASDATA Delay
15
ns
From BCLK rising edge
tTDDS
DSDATA1 Setup
15
ns
To BCLK falling edge
tTDDH
DSDATA1 Hold
15
From BCLK falling edge
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
AAUXDATA Setup
10
ns
To AUXBCLK rising edge
tAXDH
AAUXDATA Hold
10
ns
From AUXBCLK rising edge
tDXD
DAUXDATA Delay
10
ns
From AUXBCLK falling edge
fABP
AUXBCLK Frequency
64 × fS
ns
Slave Mode
tAXBH
AUXBCLK High
15
ns
tAXBL
AUXBCLK Low
15
ns
tAXLS
AUXLRCLK Setup
10
ns
To AUXBCLK rising edge
tAXLH
AUXLRCLK Hold
10
ns
From AUXBCLK rising edge
Master Mode
tAUXBCLK
AUXBCLK Delay
20
ns
From MCLK rising edge
tAUXLRCLK
AUXLRCLK Delay
15
ns
From AUXBCLK falling edge
MCLK
tPDR
tML
tMH
tMCLK
PD/RST
Figure 2. MCLK and PD/RST Timing


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