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NV34C04 Arkusz danych(PDF) 3 Page - ON Semiconductor

Numer części NV34C04
Szczegółowy opis  EEPROM Serial 4-Kb SPD Automotive Grade 1
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Table 5. A.C. CHARACTERISTICS (Note 6) VCC = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Standard
VCC = 1.7 V − 3.6 V
Fast
VCC = 1.7 V − 3.6 V
Fast−Plus
VCC = 2.2 V − 3.6 V
Units
Min
Max
Min
Max
Min
Max
FSCL (Note 5)
Clock Frequency
10
100
10
400
10
1,000
kHz
tHD:STA
START Condition Hold Time
4
0.6
0.26
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.50
ms
tHIGH
High Period of SCL Clock
4
0.6
0.26
ms
tSU:STA
START Condition Setup Time
4.7
0.6
0.26
ms
tHD:DI
Data In Hold Time
0
0
0
ms
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 7)
SDA and SCL Rise Time
1,000
300
120
ns
tF (Note 7)
SDA and SCL Fall Time
300
300
120
ns
tSU:STO
STOP Condition Setup Time
4
0.6
0.26
ms
tBUF
Bus Free Time Between
STOP and START
4.7
1.3
0.5
ms
tHD:DAT
Data Out Hold Time
200
3450
200
900
0
350
ns
Ti (Note 7)
Noise Pulse Filtered at SCL
and SDA Inputs
50
50
50
ns
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
Write Cycle Time
4
4
4
ms
tINIT (Notes 7, 8)
Power-up to Ready Mode
0.5
0.5
0.5
ms
tPOFF (Note 9)
Warm power cycle off time
0.2
0.2
0.2
ms
tTIMEOUT (Note 10) Detect clock low timeout
25
35
25
35
25
35
ms
5. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
time−out. The device also meets the Fast and Standard I2C specifications, except that Ti and tDH are shorter, as required by the 1 MHz Fast
Plus protocol.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tINIT is the delay between the Power−On Reset threshold (VPOR+) and the device is ready to accept commands.
9. Power−Off delay to ensure a proper Reset when the VCC drops below VPOR−
10. A timeout condition can only be ensured if SCL is driven low for tTIMEOUT(Max) or longer; then, NV34C04 is reset and ready to receive a new
START condition. NV34C04 does not reset if SCL is driven low for less than tTIMEOUT(Min). The interface will reset itself and will release the
SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out count takes place when SCL is low in the time interval between
START and STOP.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.3 x VCC, 0.7 x VCC
Output Load
Current Source: IOL = 6 mA; CL = 100 pF
Table 7. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
CIN
SDA, Pin Capacitance
VIN = 0
8
pF
Input Capacitance (other pins)
VIN = 0
6
pF


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