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AD773AJD Arkusz danych(PDF) 10 Page - Analog Devices |
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AD773AJD Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page AD773A REV. 0 –10– OUTPUT DATA FORMAT The AD773A provides both MSB and MSB outputs, delivering positive true offset binary and twos complement output data. Table II shows the AD773A’s output data format. Table II. Output Data Format Analog Input Digital Output Offset Twos VINA–VINB Binary Complement OTR ≥499.5 mV 11 1111 1111 01 1111 1111 1 499 mV 11 1111 1111 01 1111 1111 0 0 mV 10 0000 0000 00 0000 0000 0 –500 mV 00 0000 0000 10 0000 0000 0 ≤–500.5 mV 00 0000 0000 10 0000 0000 1 OUT OF RANGE An out-of-range condition exists when the analog input voltage is beyond the input range ( ±500 mV) of the converter. [Note the AD773A has a 4 clock cycle latency.] OTR (Pin 20) is set low when the analog input voltage is within the analog input range. OTR is set HIGH and will remain HIGH when the analog input voltage exceeds the input range by 1/2 LSB from the center of the ± full-scale output codes. OTR will remain HIGH until the analog input is within the input range. Note that if the input is driven beyond +1.5 V, the digital outputs may not stay at +FS, but may actually fold back to midscale. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table III is a truth table for the over/under range circuit in Figure 20. Systems requiring programmable gain conditioning prior to the AD773A can immediately detect an out of range condition, thus eliminating gain selection iterations. MSB OTR OVER = "1" UNDER = "1" MSB Figure 20. Overrange or Underrange Logic Table III. Out-of-Range Truth Table OTR MSB ANALOG INPUT IS 0 0 In Range 0 1 In Range 1 0 Underrange 1 1 Overrange GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. (Note—Figures 22–26 are not to scale.) The analog and digital grounds on the AD773A have been separated to optimize the management of return currents in a system. It is recommended that a 4-layer printed circuit board (PCB) which employs ground planes and power planes be used with the AD773A. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electro- magnetic interference (EMI) and an overall improvement in performance. It is important to design a layout which prevents noise from coupling onto the input signal. The wide input bandwidth of the AD773A permits noise outside the desired Nyquist bandwidth to be sampled along with the desired signal. This can result in a higher overall level of spurious noise in the digitized output. Digital signals should not be run in parallel with the circuitry. It is also suggested that the traces associated with VINA and VINB be the same length. Separate analog and digital grounds should be joined together directly under the AD773A (see Figure 24). A solid ground plane under the AD773A is also acceptable if care is taken in the management of the power and ground return currents. A general “rule-of-thumb” for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. POWER SUPPLY DECOUPLING The analog and digital supplies of the AD773A have been separated to prevent the typically large transients associated with digital circuitry from coupling into the analog supplies (AVDD, AVSS). Each analog power supply pin should be decoupled with a 0.1 µF capacitor located as close to the pin as possible. Additionally, 0.22 µF capacitors for the DRV DD and DVDD supplies are required to adequately suppress high frequency noise. For optimal performance, surface-mount capacitors are recommended. The inductance associated with the leads of through-hole ceramic capacitors typically render them ineffective at higher frequencies. A complete system will also incorporate tantalum capacitors in the 10–100 µF range to decouple low frequency noise and ferrite beads to limit high frequency noise. The digital supplies have also been separated into DRVDD and DVDD. The DRVDD pins provide power for the digital output drivers of the AD773A and are likely to contain high energy transients. Pin 22 should be decoupled directly to Pin 21 (DRGND) and Pin 7 should be decoupled directly to Pin 8 (DRGND) to minimize the length of the return path for these transients. A single +5 V supply is all that is required for DRVDD and DVDD, but decoupling DVDD with an RC filter network is suggested (see Figure 21). |
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