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MC1401A Arkusz danych(PDF) 4 Page - List of Unclassifed Manufacturers

Numer części MC1401A
Szczegółowy opis  Advanced Brushless Motor Control Chipset
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4
Electrical Characteristics
Overview
The MC1231A consists of two 68 pin PLCC's both fabricated in CMOS.
The Peripheral Input/Output IC (I/O chip) is responsible for interfacing
to the host processor and to the position input encoders. The Command
Processor IC (CP chip) is responsible for all host command, trajectory,
servo, and commutation computations, as well as for outputting the
PWM and DAC signals.
The following figure shows a typical system block diagram, along with
the pin connections between the I/O chip and the CP chip.
Encoder
(1-2 axis)
Host
Processor
CP
I/O
Data4-11
I/OAddr0-3
I/OWrite
I/OCntrl0-3
ClkOut
Amplifier
(1-2 axis)
Motor
(4 axis)
Hall Sensors
(1 - 2 axis)
The CP and I/O chips function together as one integrated motion
processor. The major components connected to the chip set are the
Encoder (2, or 1 axes), (optionally) the motor Hall-sensors (2 or 1 axes),
the motor amplifier (2, or 1 axes), and the host processor.
The encoder signals are input to the I/O chip in quadrature format. Two
signals encode the position, and an optional index signal contains a
once-per-rotation locating signal.
Hall sensors may be connected to the chipset to provide phase
initialization information, although this is not required. Three Hall sensor
signals are input per axis.
The chipset's motor output signals are connected to the motor amplifier.
Two types of output are provided; PWM (pulse width modulation), and
DAC-compatible signals used with an external DAC (digital to analog
converter). Because the output signals are commutated, more than one
motor output signal will be output per axis. See Theory of Operations
section on sinusoidal motor commutation for details.
The host processor is interfaced via an 8-bit bi-directional bus and
various control signals. Host communication is coordinated by a
ready/busy signal, which indicates when communication is allowed.
Interconnections between the two chips consist of a data bus and
various control and synchronization signals. The following table
summarizes the signals that must be interconnected for the chipset to
function properly. For each listed signal the I/O chip pin on the left side
of the table is directly connected to the pin to the right.
I/O Chip Signal
Name
I/O Chip
Pin
CP Chip
Signal Name
CP Chip
Pin
CPData4
18
Data4
50
CPData5
5
Data5
49
CPData6
6
Data6
46
CPData7
7
Data7
43
CPData8
8
Data8
40
CPData9
17
Data8
39
CPData10
3
Data10
36
CPData11
1
Data11
35
CPAddr0
68
I/OAddr0
28
CPAddr1
27
I/OAddr1
9
CPAddr2
29
I/OAddr2
6
CPAddr3
12
I/OAddr3
5
CPCntr0
20
I/OCntr0
16
CPCntr1
36
I/OCntr1
18
CPCntr2
22
I/OCntr2
68
CPCntr3
63
I/OCntr3
67
CPWrite
2
I/OWrite
15
CPClk
46
ClkOut
19
For a complete description of all pins see the 'Pin Descriptions'
section of this manual.
Absolute Maximum Ratings
Unless otherwise stated, all electrical specifications are for both
the I/O and CP chips.
Storage Temperature, Ts.....................-55 deg. C to +150 deg. C
Supply Voltage, Vcc.............................-0.3 V to +7.0 V
Power Dissipation, Pd..........................650 mW (I/O and CP
combined)
Operating Ratings
Operating Temperature, Ta .................0 deg. C to +70 deg. C
Nominal Clock Frequency, Fclk ...........25.0 Mhz
Supply Voltage, Vcc.............................4.75 V to 5.25 V
* Industrial and Military operating ranges also available. Contact your
PMD representative for more information.


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