Zakładka z wyszukiwarką danych komponentów |
|
ADP3188 Arkusz danych(PDF) 11 Page - Analog Devices |
|
ADP3188 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 16 page ADP3418 Rev. B | Page 11 of 16 The MOSFET vendor should provide a maximum voltage slew rate at drain current rating such that this can be designed around. Once you have this specification, the next step is to determine the maximum current you expect to see in the MOSFET. This can be done with the following equation: () OUT MAX MAX OUT DC MAX L f D V VCC phase per I I × × − + = ) ( (5) Here, DMAX is determined for the VR controller being used with the driver. Please note this current gets divided roughly equally between MOSFETs if more than one is used (assume a worst- case mismatch of 30% for design margin). LOUT is the output inductor value. When producing your design, there is no exact method for calculating the dV/dt due to the parasitic effects in the external MOSFETs as well as the PCB. However, it can be measured to determine if it is safe. If it appears the dV/dt is too fast, an optional gate resistor can be added between DRVH and the high-side MOSFETs. This resistor will slow down the dV/dt, but it will also increase the switching losses in the high-side MOSFETs. The ADP3418 has been optimally designed with an internal drive impedance that will work with most MOSFETs to switch them efficiently yet minimize dV/dt. However, some high-speed MOSFETs may require this external gate resistor depending on the currents being switched in the MOSFET. Low-Side (Synchronous) MOSFETs The low-side MOSFETs are usually selected to have a low on- resistance to minimize conduction losses. This usually implies a large input gate capacitance and gate charge. The first concern is to make sure the power delivery from the ADP3418’s DRVL does not exceed the thermal rating of the driver (see the Flex- mode controller data sheet for details). The next concern for the low-side MOSFETs is based on preventing them from inadvertently being switched on when the high-side MOSFET turns on. This occurs due to the drain- gate (Miller, also specified as Crss) capacitance of the MOSFET. When the drain of the low-side MOSFET is switched to VCC by the high-side turning on (at a rate dV/dt), the internal gate of the low-side MOSFET will be pulled up by an amount roughly equal to VCC × (Crss/Ciss). It is important to make sure this does not put the MOSFET into conduction. Another consideration is the non-overlap circuitry of the ADP3418 which attempts to minimize the non-overlap period. During the state of the high-side turning off to low-side turning on, the SW pin is monitored (as well as the conditions of SW prior to switching) to adequately prevent overlap. However, during the low-side turn off to high-side turn on, the SW pin does not contain information for determining the proper switching time, so the state of the DRVL pin is monitored to go below one sixth of VCC and then a delay is added. But due to the Miller capacitance and internal delays of the low-side MOSFET gate, one must ensure the Miller to input capacitance ratio is low enough and the low-side MOSFET internal delays are not large enough to allow accidental turn on of the low-side when the high-side turns on. A spreadsheet is available from ADI that will assist the designer in the proper selection of low-side MOSFETs. |
Podobny numer części - ADP3188 |
|
Podobny opis - ADP3188 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |