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CS42528 Arkusz danych(PDF) 6 Page - Cirrus Logic

Numer części CS42528
Szczegółowy opis  114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
Download  91 Pages
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42528 Arkusz danych(HTML) 6 Page - Cirrus Logic

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CS42528
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LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................... 26
Table 2. Common PLL Output Clock Frequencies........................................................................ 26
Table 3. Slave Mode Clock Ratios ................................................................................................26
Table 4. Serial Audio Port Channel Allocations............................................................................. 27
Table 5. DAC De-Emphasis .......................................................................................................... 50
Table 6. Receiver De-Emphasis.................................................................................................... 50
Table 7. Digital Interface Formats ................................................................................................. 51
Table 8. ADC One-Line Mode ....................................................................................................... 51
Table 9. DAC One-Line Mode ....................................................................................................... 51
Table 10. RMCK Divider Settings.................................................................................................. 53
Table 11. OMCK Frequency Settings............................................................................................ 54
Table 12. Master Clock Source Select .......................................................................................... 54
Table 13. AES Format Detection................................................................................................... 55
Table 14. Receiver Clock Frequency Detection ............................................................................ 56
Table 15. Example Digital Volume Settings .................................................................................. 59
Table 16. ATAPI Decode............................................................................................................... 61
Table 17. Example ADC Input Gain Settings ................................................................................ 62
Table 18. TXP Output Selection.................................................................................................... 63
Table 19. Receiver Input Selection ............................................................................................... 64
Table 20. Auxiliary Data Width Selection ...................................................................................... 67
Table 21. PLL External Component Values .................................................................................. 81
Table 22. Revision History .......................................................................................................... 90


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