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AD1837A Arkusz danych(PDF) 4 Page - Analog Devices

Numer części AD1837A
Szczegółowy opis  2 ADC, 8 DAC, 96 kHz, 24-Bit Codec
Download  24 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD1837A Arkusz danych(HTML) 4 Page - Analog Devices

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REV. A
AD1837A
–4–
TIMING SPECIFICATIONS
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
MCLK High
15
ns
tML
MCLK Low
15
ns
tPDR
PD/RST Low
20
ns
SPI
® PORT
tCCH
CCLK High
40
ns
tCCL
CCLK Low
40
ns
tCCP
CCLK Period
80
ns
tCDS
CDATA Setup
10
ns
To CCLK Rising Edge
tCDH
CDATA Hold
10
ns
From CCLK Rising Edge
tCLS
CLATCH Setup
10
ns
To CCLK Rising Edge
tCLH
CLATCH Hold
10
ns
From CCLK Rising Edge
tCOE
COUT Enable
15
ns
From CLATCH Falling Edge
tCOD
COUT Delay
20
ns
From CCLK Falling Edge
tCOTS
COUT Three-State
25
ns
From CLATCH Rising Edge
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
tDBH
DBCLK High
60
ns
tDBL
DBCLK Low
60
ns
fDB
DBCLK Frequency
64
fS
tDLS
DLRCLK Setup
10
ns
To DBCLK Rising Edge
tDLH
DLRCLK Hold
10
ns
From DBCLK Rising Edge
tDDS
DSDATA Setup
10
ns
To DBCLK Rising Edge
tDDH
DSDATA Hold
10
ns
From DBCLK Rising Edge
Packed 128/256 Modes (Slave)
tDBH
DBCLK High
15
ns
tDBL
DBCLK Low
15
ns
fDB
DBCLK Frequency
256
fS
tDLS
DLRCLK Setup
10
ns
To DBCLK Rising Edge
tDLH
DLRCLK Hold
10
ns
From DBCLK Rising Edge
tDDS
DSDATA Setup
10
ns
To DBCLK Rising Edge
tDDH
DSDATA Hold
10
ns
From DBCLK Rising Edge
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
tABD
ABCLK Delay
25
ns
From MCLK Rising Edge
tALD
ALRCLK Delay
5
ns
From ABCLK Falling Edge
tABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge
Normal Mode (Slave)
tABH
ABCLK High
60
ns
tABL
ABCLK Low
60
ns
fAB
ABCLK Frequency
64
fS
tALS
ALRCLK Setup
5
ns
To ABCLK Rising Edge
tALH
ALRCLK Hold
15
ns
From ABCLK Rising Edge
tABDD
ASDATA Delay
15
ns
From ABCLK Falling Edge
Packed 128/256 Mode (Master)
tPABD
ABCLK Delay
40
ns
From MCLK Rising Edge
tPALD
LRCLK Delay
5
ns
From ABCLK Falling Edge
tPABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge


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