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CS18LV10245EI Arkusz danych(PDF) 3 Page - List of Unclassifed Manufacturers

Numer części CS18LV10245EI
Szczegółowy opis  HIgh Speed Super Low Power SRAM
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CS18LV10245EI Arkusz danych(HTML) 3 Page - List of Unclassifed Manufacturers

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High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 3
PIN DESCRIPTIONS
Name
Function
A0-A16
Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
/CE
Chip Enable Input
CE2
Chip Enable 2 Input
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active,
the device is deselected and is in a standby power mode. The DQ pins will be
in the high impedance state when the device is deselected.
/WE
Write Enable Input
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Output Enable Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0-DQ7
Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
MODE
/WE
/CE
CE2
/OE
DQ0~7
Vcc Current
X
H
X
X
Not
Selected
X
X
L
X
High Z
ICCSB, ICCSB1
Output
Disabled
H
L
H
H
High Z
ICC
Read
H
L
H
L
DOUT
ICC
Write
L
L
H
X
DIN
ICC


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