TC9204M
Preliminary Data Sheet
4-Port 10/100/1000 Smart Ethernet Switch
Features
Stand Alone Switch On A Chip
4 Ethernet 10/100/1000 ports
MII/GMII interface for all ports
Four Classes of Service (CoS) selectable for
each port and/or checked via IP Header and
802.1Q VLAN Tag
Support 4 port-based VLANs
Maximum throughput (wire speed), non
head-of-line blocking architecture
Embedded SSRAM for packet buffer /
address table, no external memory required
8K MAC address table
25 MHz crystal input only
Each port is configurable to 10 full/half duplex,
100 full/half duplex and 1000 full duplex mode
Flow-control ability is able to set for both full
and half duplex mode
Broadcast throttling
Port Mirroring
Serial EEPROM Interface, EEPROM is optional
MDIO master for PHY configuration / polling
0.18 micron technology
2.0V and 3.3V dual voltage power supply
Packaged in PQFP 208
General Description
TC9204M is a fully integrated 4-Port 10/100/1000
smart Ethernet switch controller designed for low
cost and high performance solutions. The chip
embeds necessary SSRAM for packet buffering
and MAC address table. It provides MII / GMII
interface for all ports.
A store-and-forward switching method using a
non-blocking architecture is implemented within
TC9204M to improve the availability and
bandwidth. The chip embeds SSRAM packet
buffer, which it supports normal and priority
queues for each transmission port.
TC9204M provides evolved CoS with four levels
of priority. The priority can be checked via layer 2
(802.1Q VLAN Tagging) and/or layer 3 (IP Header
TOS bits) packets. Port based priority is also
provided to ensure transmission with precedence
for all packets incoming from selected port(s).
This
feature allows
improved support
for
multimedia applications.
The chip embeds IEEE 802.3 MAC functions for
each port and these functions support full and half
duplex modes for both 10 and 100 Mbits/s data
rates and full duplex for 1000 Mbit/s. Each port
includes dedicated receive and transmit FIFOs
with necessary logic to implement flow control for
both full and half duplex modes. TC9204M uses
IEEE 802.3x frame based flow control for full
duplex and backpressure for half duplex.
TC9204M handles an 8K address-lookup table
with searching, self-learning, and automatic aging
at very high speed and excellent address space
coverage. Forwarding rules are implemented
according to IEEE 802.1D specifications. Filtering
capabilities for bad packets and packets with
Reserved Group Address DA are also provided.
A port mirror feature, optionally including bad frames,
can be used for debugging network problems.
The pin configuration interface comprises 40
configurations, which are shared with GMII output
pins by latching the configuration data during
reset. An external EEPROM device can also be
used to configure the TC9204M at power-up. With
reference to pin configuration interface, the
EEPROM
extends
the
chip’s
configuration
capability with new features and enables a
jumper-less configuration mode using a parallel
interface for reprogramming. A virtual internal
EEPROM mode is also provided to enable the
use of the programming interface in the absence
of external EEPROM. TC9204M can make
effective use by most of its features using only the
pin configuration interface.
TC9204M includes a physical layer configuration /
polling entity, which it is use to configure the phy
functions and to monitor the physical layer
transceiver’s speed, duplex mode, link status and
full duplex flow control ability for each port. The
chip provides four modes for phy configurations,
which these modes include auto-negotiation
disable procedure for 10/100 speed modes. The
phy configuration information is stored in
EEPROM setting.
Confidential.
1/49
July 29, 2003
Copyright © 2003, IC Plus Corp.
TC9204M-DS-R05
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