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ADP3168JRU-REEL Arkusz danych(PDF) 9 Page - Analog Devices |
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ADP3168JRU-REEL Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 24 page ADP3168 Rev. B | Page 9 of 24 THEORY OF OPERATION The ADP3168 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10 specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter would place high thermal demands on system components such as inductors and MOSFETs. The multimode control of the ADP3168 ensures a stable, high performance topology for • Balancing currents and thermals between phases • High speed response at the lowest possible switching frequency and output decoupling • Minimizing thermal switching losses due to lower frequency operation • Tight load-line regulation and accuracy • High current output resulting from having up to a 4-phase operation • Reduced output ripple due to multiphase cancellation • PC board layout noise immunity • Ease of use and design due to independent component selection • Flexibility in operation for tailoring design to low cost or high performance NUMBER OF PHASES The number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3168 operates as a 4-phase PWM controller. Grounding the PWM4 pin programs 3-phase operation; grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3168 is enabled, the controller outputs a voltage on PWM3 and PWM4 of approximately 550 mV. An internal comparator checks each pin’s voltage vs. a threshold of 400 mV. If the pin is grounded, the voltage is below the threshold and the phase is disabled. The output resistance of the PWM pin is approximately 5 kΩ during this detection time. Any external pull-down resistance connected to the PWM pin should be at least 25 kΩ to ensure proper operation. The phase detection is made during the first two clock cycles of the internal oscillator. After this time, if the PWM output is not grounded, the 5 kΩ resistance is removed and switches between 0 V and 5 V. If the PWM output was grounded, it remains off. The PWM outputs become logic-level devices once normal operation starts. The detection is normal and is intended for driving external gate drivers such as the ADP3418. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at any given time for overlapping phases. MASTER CLOCK FREQUENCY The clock frequency of the ADP3168 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3168 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amp- lifier to maintain a worst-case specification of ±10 mV differ- ential sensing error with a VID input of 1.6000 V over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 90 µA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage. OUTPUT CURRENT SENSING The ADP3168 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET. This amplifier can be configured several ways, depending on the objectives of the system: • Output inductor ESR sensing without thermistor for lowest cost • Output inductor ESR sensing with thermistor for improved accuracy with tracking of inductor temperature • Sense resistors for most accurate measurements |
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