KM718V987 datasheet(11/21 Pages) SAMSUNG

Numer części	KM718V987

Szczegółowy opis	256Kx36 & 512Kx18 Synchronous SRAM

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Producent	SAMSUNG [Samsung semiconductor]

Strona internetowa	http://www.samsung.com/Products/Semiconductor

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KM718V987

256Kx36 & 512Kx18 Synchronous SRAM

- 11 -

Rev 4.0

May 1999

KM736V887

AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0

°C to +70°C)

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and

CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

PARAMETER

SYMBOL

-7

-8

-9

-10

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle Time

tCYC

8.5

-

10

-

12

-

12

-

ns

Clock Access Time

tCD

-

7.5

-

8.5

-

9.0

-

10

ns

Output Enable to Data Valid

tOE

-

3.5

-

3.5

-

3.5

-

3.5

ns

Clock High to Output Low-Z

tLZC

2.5

-

2.5

-

2.5

-

2.5

-

ns

Output Hold from Clock High

tOH

2.5

-

2.5

-

2.5

-

2.5

-

ns

Output Enable Low to Output Low-Z

tLZOE

0

-

0

-

0

-

0

-

ns

Output Enable High to Output High-Z

tHZOE

-

3.5

-

3.5

-

3.5

-

4.0

ns

Clock High to Output High-Z

tHZC

-

4.0

-

5.0

-

5.0

-

6.0

ns

Clock High Pulse Width

tCH

2.5

-

3.0

-

3.0

-

3.0

-

ns

Clock Low Pulse Width

tCL

2.5

-

3.0

-

3.0

-

3.0

-

ns

Address Setup to Clock High

tAS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Address Status Setup to Clock High

tSS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Data Setup to Clock High

tDS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Write Setup to Clock High (GW, BW, WEX)

tWS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Address Advance Setup to Clock High

tADVS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Chip Select Setup to Clock High

tCSS

2.0

-

2.0

-

2.0

-

2.0

-

ns

Address Hold from Clock High

tAH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Address Status Hold from Clock High

tSH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Data Hold from Clock High

tDH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Write Hold from Clock High (GW, BW, WEX)

tWH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Address Advance Hold from Clock High

tADVH

0.5

-

0.5

-

0.5

-

0.5

-

ns

Chip Select Hold from Clock High

tCSH

0.5

-

0.5

-

0.5

-

0.5

-

ns

ZZ High to Power Down

tPDS

2

-

2

-

2

-

2

-

cycle

ZZ Low to Power Up

tPUS

2

-

2

-

2

-

2

-

cycle

Output Load(B),

(for tLZC, tLZOE, tHZOE & tHZC)

Dout

353

Ω / 1538Ω

5pF*

+3.3V for 3.3V I/O

319

Ω / 1667Ω

Fig. 1

* Including Scope and Jig Capacitance

Output Load(A)

Dout

Zo=50

Ω

RL=50

Ω

VL=1.5V for 3.3V I/O

VDDQ/2 for 2.5V I/O

/+2.5V for 2.5V I/O

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