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ADSP-TS202SABP-X Arkusz danych(PDF) 8 Page - Analog Devices |
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ADSP-TS202SABP-X Arkusz danych(HTML) 8 Page - Analog Devices |
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8 / 40 page  Rev. PrB | Page 8 of 40 | December 2003 ADSP-TS202S Preliminary Technical Data LINK PORTS (LVDS) The DSP’s four full-duplex link ports each provide additional four-bit receive and four-bit transmit I/O capability, using Low- Voltage, Differential-Signal (LVDS) technology. With the abil- ity to operate at a double data rate—latching data on both the rising and falling edges of the clock—running at 500 MHz, each link port can support up to 500M bytes per second per direc- tion, for a combined maximum throughput of 4G bytes per second. The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing point- to-point interprocessor communications. Applications can also use the link ports for booting. Each link port has its own triple-buffered quad-word input and double-buffered quad-word output registers. The DSP’s core can write directly to a link port’s transmit register and read from a receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedi- cated link port DMA channels. Each link port direction has three signals that control its opera- tion. For the transmitter, LxCLKOUT is the output transmit clock, LxACKI is the handshake input to control the data flow, and the LxBCMPO output indicates that the block transfer is complete. For the receiver, LxCLKIN is the input receive clock, LxACKO is the handshake output to control the data flow, and Figure 4. ADSP-TS202S Shared Memory Multiprocessing System CLKS/REFS ADDR31–0 DATA63–0 BR1 BR7–2,0 ADDR31–0 DATA63–0 BR0 BR7–1 BMS CONTROL ADSP-TS202S #0 CONTROL ADSP-TS202S #1 ADSP-TS202S #7 ADSP-TS202S #6 ADSP-TS202S #5 ADSP-TS202S #4 ADSP-TS202S #3 ADSP-TS202S #2 RESET RST_IN ID2–0 CLKS/REFS SCLK_VREF VREF SCLK SCLKRAT2–0 000 CLOCK REFERENCE ADDR DATA HOST PROCESSOR INTERFACE (OPTIONAL) ACK GLOBAL MEMORY AND PERIPHERALS (OPTIONAL) OE ADDR DATA CS ADDR DATA BOOT EPROM (OPTIONAL) RD MS1–0 ACK ID2–0 001 HBG HBR BOFF BRST CS WE WRH/L SDRAM MEMORY (OPTIONAL) MSSD3–0 IORD IOEN RAS CAS LDQM HDQM SDWE SDCKE SDA10 CS RAS CAS DQM WE CKE A10 ADDR DATA CLK MSH DMAR3–0 DPA CPA LINK DEVICES (4 MAX) (OPTIONAL) LxCLKINP/N LxACKO LxDATI3–0P/N LxBCMPI LxBCMPO LxDATO3–0P/N LxCLKOUTP/N LxACKI TMR0E BM CONTROLIMP1–0 LINK IRQ3–0 FLAG3–0 LINK RST_IN BUSLOCK CLOCK DS2–0 IOWR JTAG POR_IN RST_OUT REFERENCE LINK DEVICES |
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