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DAC53401 Dane(HTML) 35 Page - Texas Instruments

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Numer części DAC53401
Szczegółowy opis  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
Pobierz  42 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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DAC53401 Datasheet(Arkusz danych) 35 Page - Texas Instruments

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P
DAC
FB
3
V
V
R
10 A
35
DAC53401, DAC43401
www.ti.com
SLASES7 – JULY 2019
Product Folder Links: DAC53401 DAC43401
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Copyright © 2019, Texas Instruments Incorporated
Typical Applications (continued)
9.2.2.2 Detailed Design Procedure
The DACx3401 features a Hi-Z power-down mode that is set by default at power-up, unless the device is
programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the
SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers
up, make sure to power up the device at the same output as VFB (that is 0.6 V). This configuration makes sure
there is no current through R3 even at power-up. To achieve ±10% margin-high and margin-low conditions, the
DAC must draw ±10% of the nominal current (that is, ±10 µA). In order to calculate the value of R3, first decide
the DAC output range, making sure to avoid the codes near zero scale and full-scale for safe operation in the
linear region. A DAC output of 20 mV can be safely considered as the minimum output and (1.8 V – 0.6 V – 20
mV = 1.18 V) can be considered as the maximum output. When the DAC output is at 20 mV, the power supply
goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to margin low. The value of
R3 can be calculated by Equation 7. For the previous values, R3 = 58 kΩ.
(7)
The DACx3401 have a slew rate feature that is used to toggle between margin high, margin low, and nominal
outputs with a defined slew rate. See the GENERAL_CONFIG register description for the slew rate setting
details.
The pseudocode for getting started with a power-supply control application is as follows:
//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Power-up the device, enable internal reference with 1x output span
//CODE_STEP: 1-bit, SLEW_RATE: 12µs
WRITE GENERAL_CONFIG(0xD1), 0x11, 0x84
//Write DAC code (12-bit aligned) for nominal output
//For a 1.8V output range, the 10-bit Hex code for 20mV is 0x0B. With 12-bit alignment, it becomes 0x2C
WRITE DAC_DATA(0x21), 0x0F, 0xFC
//Write DAC code (12-bit aligned) for margin-high output
WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x7C
//Write DAC code (12-bit aligned) for margin-low output
WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x2C
//Trigger margin-high output
WRITE TRIGGER(0xD3), 0x00, 0x80
//Trigger margin-low output
WRITE TRIGGER(0xD3), 0x00, 0x40
//Write back DAC code (12-bit aligned) for nominal output
WRITE DAC_DATA(0x21), 0x0F, 0xFC


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