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DAC53401 Dane(HTML) 6 Page - Texas Instruments

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Numer części DAC53401
Szczegółowy opis  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
Pobierz  42 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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DAC53401 Datasheet(Arkusz danych) 6 Page - Texas Instruments

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6
DAC53401, DAC43401
SLASES7 – JULY 2019
www.ti.com
Product Folder Links: DAC53401 DAC43401
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ZO
VOUT + VFB dc output
impedance(2)
At startup, measured when DAC output is disabled
and held at VDD / 2 for VDD = 5.5 V
0.5
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale;
VDD = 5 V ±10%
0.25
mV/V
DYNAMIC PERFORMANCE
tsett
Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
10
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
20
Slew rate
VDD = 5.5 V
1
V/µs
Power on glitch magnitude
At startup (DAC output disabled), RL = 5 kΩ, CL = 200
pF
110
mV
At startup (DAC output disabled), RL = 100 kΩ
400
Output enable glitch
magnitude
DAC output disabled to enabled (DAC registers at
zero scale, RL = 100 kΩ
400
mV
Vn
Output noise voltage (peak to
peak)
0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
34
µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at
midscale, VDD = 5.5 V
70
Output noise density
Measured at 1 kHz, DAC at midscale, VDD = 5.5 V
0.2
µV/
√Hz
Internal VREF, gain = 4x,, measured at 1 kHz, DAC at
midscale, VDD = 5.5 V
0.7
Power supply rejection ratio
(ac)
Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine
wave superimposed on power supply voltage, DAC at
midscale
–71
dB
Code change glitch impulse
±1 LSB change around mid code (including
feedthrough)
10
nV-s
Code change glitch impulse
magnitude
±1 LSB change around mid code (including
feedthrough)
25
mV
EEPROM
Endurance
–40°C
≤ TA ≤ 85°C
20000
Cycles
1000
Data retention
TA = 25°C
50
Years
EEPROM programming write
cycle time(2)
5
10
15
ms
DIGITAL INPUTS
Digital feedthrough
DAC output static at midscale, fast+ mode, SCL
toggling
20
nV-s
Pin capacitance
Per pin
10
pF
POWER REQUIREMENTS
Load capacitor - CAP pin(2)
0.5
15
µF
IDD
Current flowing into VDD
Normal mode, DACs at full scale, digital pins static
0.5
0.8
mA
DAC power-down, internal reference power down
80
µA


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