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ADS8381IBPFBTG4 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS8381IBPFBTG4 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 35 page ADS8381 SLAS364D − APRIL 2002 − REVISED FEBRUARY 2005 www.ti.com 7 TIMING CHARACTERISTICS All specifications typical at −40 °C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER MIN TYP MAX UNIT tCONV Conversion time 1.4 µs tACQ Acquisition time 0.3 µs tHOLD Sampling capacitor hold time 25 ns tpd1 CONVST low to conversion started (BUSY high) 50 ns tpd2 Propagation delay time, end of conversion to BUSY low 25 ns tpd3 Propagation delay time, from start of conversion (internal state) to rising edge of BUSY 25 ns tw1 Pulse duration, CONVST low 40 600 ns tsu1 Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps tw3 Pulse duration, BUSY signal low Min(tACQ) µs tw4 Pulse duration, BUSY signal high 1.4 µs th1 Hold time, first data bus transition (CS low for read cycle, or RD or BYTE or BUS 18/16 input changes) after CONVST low 40 600 ns td1 Delay time, CS low to RD low 0 ns tsu2 Setup time, RD high to CS high 0 ns tw5 Pulse duration, RD low 50 ns ten Enable time, RD low (or CS low for read cycle) to data valid 30 ns td2 Delay time, data hold from RD high 10 ns td3 Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid 10 30 ns tw6 Pulse duration, RD high time 20 ns tw7 Pulse duration, CS high time 20 ns th2 Hold time, last CS rising edge or changes of RD, BYTE, or BUS18/16 to CONVST falling edge 125 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) ns td4 Delay time, BYTE edge to BUS18/16 edge skew 0 ns tsu3 Setup time, BYTE or BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 transition to RD falling edge 10 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus 30 ns td5 Delay time, BUSY low to MSB data valid delay time 40 ns tsu5 Setup time, BYTE transition to next BYTE transition, or BUS18/16 transition to next BUS18/16 transition 50 ns tsu(AB) Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is used to abort). 70 1000 ns tf(CONVST) Falling time, (CONVST falling edge) 10 30 ns tsu6 Setup time, CS falling edge to CONVST falling edge when RD = 0 125 ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2 except for CONVST. (2) See timing diagrams. (3) All timing are measured with 10 pF equivalent loads on all data bits and BUSY pins. |
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