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COP87L88RG Arkusz danych(PDF) 4 Page - National Semiconductor (TI) |
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COP87L88RG Arkusz danych(HTML) 4 Page - National Semiconductor (TI) |
4 / 40 page Absolute Maximum Ratings (Note) If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Supply Voltage (VCC)7V Voltage at Any Pin b 03V to VCC a 03V Total Current into VCC Pin (Source) 100 mA Total Current out of GND Pin (Sink) 110 mA Storage Temperature Range b 65 Cto a140 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings DC Electrical Characteristics b40 C s TA s a85 C unless otherwise specified Parameter Conditions Min Typ Max Units Operating Voltage 27 55 V Power Supply Ripple (Note 1) Peak-to-Peak 01 VCC V Supply Current (Note 2) CKI e 10 MHz VCC e 55V tc e 1 ms 165 mA CKI e 4 MHz VCC e 40V tc e 25 ms 65 mA HALT Current (Note 3) VCC e 55V CKI e 0 MHz 12 m A VCC e 40V CKI e 0 MHz 8 m A IDLE Current CKI e 10 MHz VCC e 55V tc e 1 ms 35 mA CKI e 1 MHz VCC e 40V tc e 10 ms 07 mA Input Levels RESET Logic High 08 VCC V Logic Low 02 VCC V CKI (External and Crystal Osc Modes) Logic High 07 VCC V Logic Low 02 VCC V All Other Inputs Logic High 07 VCC V Logic Low 02 VCC V Hi-Z Input Leakage VCC e 55V b 2 a 2 m A Input Pullup Current VCC e 55V 40 250 m A G and L Port Input Hysteresis 005 VCC 035 VCC V Output Current Levels D Outputs Source VCC e 45V VOH e 33V 04 mA Sink (Note 4) VCC e 45V VOL e 1V 10 mA All Others Source (Weak Pull-Up Mode) VCC e 45V VOH e 27V 10 100 m A Source (Push-Pull Mode) VCC e 45V VOH e 33V 04 mA Sink (Push-Pull Mode) VCC e 45V VOL e 04V 16 mA TRI-STATE Leakage VCC e 55V b 2 a 2 m A Allowable SinkSource Current per Pin D Outputs (Sink) 15 mA All others 3mA Maximum Input Current TA e 25 C g 100 mA without Latchup (Note 5) RAM Retention Voltage Vr 500 ns Rise and Fall Time (Min) 2 V Input Capacitance 7pF Load Capacitance on D2 1000 pF Note 1 Rate of voltage change must be less then 05 Vms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high Test conditions All inputs tied to VCC L and G ports in the TRI-STATE mode and tied to ground all outputs low and tied to ground The clock monitor is disabled Note 4 The user must guarantee that D2 pin does not source more than 10 mA during RESET If D2 sources more than 10 mA during reset the device will go into programming mode Note 5 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V http www nationalcom 4 |
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