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ADC08D1500CIYB Arkusz danych(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC08D1500CIYB
Szczegółowy opis  High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC08D1500CIYB Arkusz danych(HTML) 7 Page - National Semiconductor (TI)

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Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A,VDR)
2.2V
Voltage on Any Input Pin
−0.15V to (V
A
+0.15V)
Ground Difference
|GND - DR GND|
0V to 100 mV
Input Current at Any Pin (Note 3)
±25 mA
Package Input Current (Note 3)
±50 mA
Power Dissipation at T
A
≤ 85˚C
2.0 W
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
2500V
250V
Soldering Temperature, Infrared,
10 seconds, (Note 5), (Applies
to standard plated package only)
235˚C
Storage Temperature
−65˚C to +150˚C
Operating Ratings (Notes 1, 2)
Ambient Temperature Range
−40˚C
≤ T
A
≤ +85˚C
Supply Voltage (V
A)
+1.8V to +2.0V
Driver Supply Voltage (V
DR)
+1.8V to V
A
Analog Input Common Mode
Voltage
V
CMO ±50mV
V
IN+, VIN- Voltage Range
(Maintaining Common Mode)
200mV to V
A
Ground Difference
(|GND - DR GND|)
0V
CLK Pins Voltage Range
0V to V
A
Differential CLK Amplitude
0.4V
P-P to 2.0VP-P
Package Thermal Resistance
Package
θ
JA
θ
JC (Top of
Package)
θ
J-PAD
(Thermal
Pad)
128-Lead
Exposed Pad
LQFP
26˚C / W
10˚C / W
2.8˚C / W
Converter Electrical Characteristics
NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.
The specifications in this section cannot be guaranteed until device characterization has taken place. The following
specifications apply after calibration for V
A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P,CL
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
CLK = 1.5 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-
Extended Control Mode, SDR Mode, R
EXT = 3300
±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for T
A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
INL
Integral Non-Linearity (Best fit)
DC Coupled, 1MHz Sine Wave
Overanged
±0.3
±TBD
LSB (max)
DNL
Differential Non-Linearity
DC Coupled, 1MHz Sine Wave
Overanged
±0.15
±TBD
LSB (max)
Resolution with No Missing
Codes
8
Bits
V
OFF
Offset Error
-0.45
−TBD
TBD
LSB (min)
LSB (max)
V
OFF_ADJ
Input Offset Adjustment Range
Extended Control Mode
±45
mV
PFSE
Positive Full-Scale Error (Note
9)
−0.6
±TBD
mV (max)
NFSE
Negative Full-Scale Error (Note
9)
−1.31
±TBD
mV (max)
FS_ADJ
Full-Scale Adjustment Range
Extended Control Mode
±20
±15
%FS
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
FPBW
Full Power Bandwidth
Normal Mode (non DES)
1.7
GHz
B.E.R.
Bit Error Rate
10
-18
Error/Sample
Gain Flatness
d.c. to 500 MHz
±0.5
dBFS
d.c. to 1 GHz
±1.0
dBFS
ENOB
Effective Number of Bits
f
IN = 248 MHz, VIN = FSR − 0.5 dB
7.4
TBD
Bits (min)
f
IN = 498 MHz, VIN = FSR − 0.5 dB
7.4
TBD
Bits (min)
f
IN = 748 MHz, VIN = FSR − 0.5 dB
7.25
TBD
Bits (min)
www.national.com
7


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