Zakładka z wyszukiwarką danych komponentów |
|
ADSP-21366SCSQZENG Arkusz danych(PDF) 4 Page - Analog Devices |
|
ADSP-21366SCSQZENG Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 54 page Rev. PrA | Page 4 of 54 | September 2004 ADSP-21365/6 Preliminary Technical Data Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all opera- tions in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing ele- ments. These computation units support IEEE 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-21365/6 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data (see Figure 1 on page 1). With the ADSP-21365/6’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a sin- gle cycle. Instruction Cache The ADSP-21365/6 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21365/6’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital Figure 2. ADSP-21365/6 System Sample Configuration DAI SPI ID P SR C SPD IF SP OR T0-5 SC LK 0 SD 0A SFS0 SD 0B SR U DAI_P1 DA I_ P2 DA I_ P3 DAI_P 18 DAI _P 19 DA I_ P2 0 DAC (OPTI ONA L) ADC (OPTI ONA L) FS CLK SD AT FS CLK SD AT 3 CLOC K FLA G3-1 2 2 CLK IN XTA L CLK _CFG1-0 B OOTC FG1 -0 ADDR PARALLEL POR T RAM , ROM BOO T R OM I/O D EVI CE OE DATA WE RD WR CLKOUT ALE AD 1 5-0 LA TCH RES ET JTA G 6 ADSP -21365/6 CS FLA G0 PCG B PC GA CLK FS TIME R S |
Podobny numer części - ADSP-21366SCSQZENG |
|
Podobny opis - ADSP-21366SCSQZENG |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |