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MC10EP29 Arkusz danych(PDF) 2 Page - ON Semiconductor |
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MC10EP29 Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC10EP29, MC100EP29 http://onsemi.com 2 VBB Figure 1. 20–Lead Pinout (Top View) and Logic Diagram CLK0 D1 CLK1 17 18 16 15 14 13 12 4 35 6 7 8 9 Q0 11 10 Q0 S0 S1 VCC Q1 Q1 VEE D0 19 20 2 1 R0 VCC CLK0 D1 D0 CLK1 R1 CLK D S R Q Q CLK D R S Q Q R L L H L H TRUTH TABLE S L L L H H D L H X X X CLK Z Z X X X Q L H L H Undef Z = LOW to HIGH Transition X = Don’t Care Q H L H L Undef PIN DESCRIPTION FUNCTION ECL Differential Data Inputs ECL Reset Inputs ECL Differential Clock Inputs ECL Differential Clock Inputs ECL Set Inputs ECL Differential Data Outputs Reference Voltage Output Positive Supply Negative Supply PIN D0*, D0*; D1*, D1* R0*, R1* CLK0*, CLK0* CLK1*, CLK1* S0*, S1* Q0, Q0; Q1, Q1 VBB VCC VEE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. * Pins will default LOW when left open. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k W Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in Transistor Count 383 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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