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MC14020B Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC14020B Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14020B/D MC14020B 14-Bit Binary Counter The MC14020B 14–stage binary counter is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 14 stages of ripple–carry binary counter. The device advances the count on the negative–going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency–dividing circuits. • Fully Static Operation • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Buffered Outputs Available from stages 1 and 4 thru 14 • Common Reset Line • Pin–for–Pin Replacement for CD4020B MAXIMUM RATINGS (Voltages Referenced to VSS) (Note NO TAG) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note NO TAG) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Device Package Shipping ORDERING INFORMATION MC14020BCP PDIP–16 2000/Box MC14020BD SOIC–16 48/Rail MC14020BDR2 SOIC–16 2500/Tape & Reel 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14020BCP AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 16 14020B AWLYWW SOEIAJ–16 F SUFFIX CASE 966 1 16 MC14020B AWLYWW TSSOP–16 DT SUFFIX CASE 948F 14 020B ALYW 1 16 MC14020BDT TSSOP–16 96/Rail MC14020BF SOEIAJ–16 See Note 1. MC14020BFEL SOEIAJ–16 See Note 1. |
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