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MC14044B Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC14044B
Szczegółowy opis  CMOS MSI(Quad R-S Latches)
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Strona internetowa  http://www.onsemi.com
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MC14044B Arkusz danych(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14043B/D
MC14043B, MC14044B
CMOS MSI
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three–state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Double Diode Input Protection
Three–State Outputs with Common Enable
Outputs Capable of Driving Two Low–power TTL Loads or One
Low–Power Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
XX
= Specific Device Code
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14043BCP
PDIP–16
2000/Box
MC14043BD
SOIC–16
2400/Box
MC14043BDR2
SOIC–16
2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
140XXB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC140XXB
AWLYWW
MC14043BF
SOEIAJ–16
See Note 1.
MC14043BFEL
SOEIAJ–16
See Note 1.
MC14044BCP
PDIP–16
2000/Box
MC14044BD
SOIC–16
2400/Box
MC14044BDR2
SOIC–16
2500/Tape & Reel


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