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CS4265 Arkusz danych(PDF) 41 Page - Cirrus Logic

Numer części CS4265
Szczegółowy opis  105 dB, 24-Bit, 192 kHz Stereo Audio CODEC
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
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CS4265
DS657A2
41
6.17.2 C-Data Access Mode (Bit 5)
Function:
When cleared, the C-data buffer will operate in One-byte control port access mode. When set, the C-
data buffer will operate in Two-byte control port access mode. See “IEC60958-3 Channel Status (C)
Bit Management” on page 50.
6.18 Transmitter Control 2 - Address 12h
6.18.1 Transmitter Digital Interface Format (Bits 7:6)
Function:
The required relationship between LRCK, SCLK and SDIN for the transmitter is defined by the Trans-
mitter Digital Interface Format and the options are detailed in Table 16 and Figures 5-7.
6.18.2 Transmitter Output Driver Control (Bit 5)
Function:
When this bit is cleared, the transmitter output pin driver will be in the normal operational mode. When
set, the transmitter output pin driver will drive to a constant 0 V.
6.18.3 Transmitter Mute Control (Bit 4)
Function:
When this bit is cleared, the transmitter data will be in the normal operational mode. When set, the
transmitter will output all zero data.
6.18.4 Transmitted Validity Bit Control (Bit 3)
Function:
This bit sets the transmitted Validity bit level.
When this bit is cleared, valid linear PCM audio data is indicated. When this bit is set, invalid or non-
linear PCM audio data is indicated.
6.18.5 Transmitter Mono/Stereo Operation Control (Bit 2)
Function:
When this bit is cleared, the transmitter will operate in stereo mode. When set, the transmitter will op-
erate in mono mode with one input channel’s data output in both A and B subframes (see “IEC60958-
3 Channel Status (C) Bit Management” on page 50) and the CS data defined by the MMTCS bit (see
section 6.18.6).
7
654
32
10
Tx_DIF1
Tx_DIF0
TxOff
TxMute
V
MMT
MMTCS
MMTLR
Table 16. Transmitter Digital Interface Formats
Tx_DIF1
Tx_DIF0
Description
Format
Figure
0
0
Left Justified, up to 24-bit data (default)
0
5
01
I2S, up to 24-bit data
16
1
0
Right Justified, 16-bit Data
2
7
1
1
Right Justified, 24-bit Data
3
7


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