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MC14538BDTR2 Arkusz danych(PDF) 5 Page - ON Semiconductor |
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MC14538BDTR2 Arkusz danych(HTML) 5 Page - ON Semiconductor |
5 / 12 page MC14538B http://onsemi.com 5 OPERATING CONDITIONS External Timing Resistance RX — 5.0 — (8.) k Ω External Timing Capacitance CX — 0 — No Limit (9.) µF 8. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ.. 9. If CX > 15 µF, use discharge protection diode per Fig. 11. Figure 1. Logic Diagram (1/2 of DevIce Shown) NOTE: Pins 1, 8 and 15 must be externally grounded – + – + VDD VDD P1 RX CX 2 1 (14) (15) 4 (12) 5(11) 3 (13) A B RESET VSS N1 Vref1 C1 C2 ENABLE Vref2 ENABLE CONTROL S RESET LATCH QR QR R S R S Q Q 6 (10) 7 (9) OUTPUT LATCH Figure 2. Power Dissipation Test Circuit and Waveforms 500 pF VDD 0.1 µF CERAMIC RX RX′ CX′ VSS CX VSS Vin CX/RX A B RESET A ′ B ′ RESET ′ Q Q Q ′ Q ′ VSS CL CL CL CL 20 ns 20 ns VDD 0 V 90% 10% Vin ID |
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