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SI3016-KS Arkusz danych(PDF) 8 Page - Texas Instruments |
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SI3016-KS Arkusz danych(HTML) 8 Page - Texas Instruments |
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8 / 87 page  TMS320C54V90 EMBEDDED V.90 MODEM DSP SPRS165F − JULY 2001 − REVISED OCTOBER 2003 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TMS320C54V90 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION I/O† OSCILLATOR/TIMER PINS CLKOUT O/Z Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low. CLKMD1 CLKMD2 CLKMD3 I Clock mode external/internal input signals. CLKMD1−CLKMD3 allows you to select and configure different clock modes such as crystal, external clock, various PLL factors. X2/CLKIN I Input pin to internal oscillator from the crystal. If the internal oscillator is not being used, an external clock source can be applied to this pin. The internal machine cycle time is determined by the clock operating mode pins (CLKMD1, CLKMD2 and CLKMD3). X1 O Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. TOUT O Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low. TOUT1 I/O/Z Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is a CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI, and TOUT1 is only available when the HPI is disabled. MULTICHANNEL BUFFERED SERIAL PORT PINS BCLKR0 BCLKR1 I/O/Z Receive clock input. CLKR serves as the serial shift clock for the buffered serial port receiver. BCLKRX2 is McBSP2 transmit AND receive clock. This pin is optionally bondable as C1A (see DAA section). BDR0 BDR1 I Serial data receive input. BFSR0 BFSR1 BFSRX2 I/O/Z Frame synchronization pulse for receive input. The FSR pulse initiates the receive data process over DR. BFSRX2 is McBSP2 transit AND receive frame sync BCLKX0 BCLKX1 I/O/Z Transmit clock. CLKX serves as the serial shift clock for the buffered serial port transmitter. The CLKX pins are configured as inputs after reset. CLKX goes into the high-impedance state when OFF is low. BDX0 BDX1 O/Z Serial data transmit output. DX is placed in the high-impedance state when not transmitting, when RS is asserted or when OFF is low. BFSX0 BFSX1 I/O/Z Frame synchronization pulse for transmit output. The FSX pulse initiates the transmit data process over DX. The FSX pins are configured as inputs after reset. FSX goes into the high-impedance state when OFF is low. INTEGRATED DAA C1A I/O DAA I/O connection. C1A5V S Dedicated 5.0-V power supply for I/O pin C1A. DAAEN I DAA Enable Input. Enables the DAA when low. UART TX O UART asynchronous serial transmit data output. RX I UART asynchronous serial receive data input. † I = Input, O = Output, Z = High-impedance, S = Supply |
Podobny numer części - SI3016-KS |
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Podobny opis - SI3016-KS |
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