Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

ISL3874IK96 Arkusz danych(PDF) 4 Page - Intersil Corporation

Numer części ISL3874IK96
Szczegółowy opis  Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
Download  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL3874IK96 Arkusz danych(HTML) 4 Page - Intersil Corporation

  ISL3874IK96 Datasheet HTML 1Page - Intersil Corporation ISL3874IK96 Datasheet HTML 2Page - Intersil Corporation ISL3874IK96 Datasheet HTML 3Page - Intersil Corporation ISL3874IK96 Datasheet HTML 4Page - Intersil Corporation ISL3874IK96 Datasheet HTML 5Page - Intersil Corporation ISL3874IK96 Datasheet HTML 6Page - Intersil Corporation ISL3874IK96 Datasheet HTML 7Page - Intersil Corporation ISL3874IK96 Datasheet HTML 8Page - Intersil Corporation ISL3874IK96 Datasheet HTML 9Page - Intersil Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 33 page
background image
4
HBE0
H16
5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0).
HINTA
C6
CMOS, Output
PCI Bus Interrupt A
HRESET
D6
5V Tol, CMOS, Input PCI reset.
HFRAME
B15
5V Tol, BiDir
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
FRAME is deasserted, the PCI bus transaction is in the final data phase.
HIRDY
A15
5V Tol, CMOS, BiDir PCI initiator ready. HIRDY indicates the PCI bus initiators ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both HIRDY and
HTRDY are asserted. Until HIRDY and HTRDY are both sampled asserted, wait states are inserted.
HTRDY
A16
5V Tol, CMOS, BiDir PCI target ready. HTRDY indicates the primary bus targets ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK when both HIRDY
and HTRDY are asserted. Until both HIRDY and HTRDY are asserted, wait states are inserted.
HREQ
B7
CMOS, Output
PCI bus request. HREQ is asserted by the ISL3874 to request access to the PCI bus as an initiator.
HSERR
B16
CMOS, Output
PCI system error. HSERR is an output that is pulsed from the ISL3874 when enabled through the
command register indicating a system error has occurred. The ISL3874 need not be the target of
the PCI cycle to assert this signal. When HSERR is enabled in the control register, this signal also
pulses, indicating that an address parity error has occurred on a CardBus interface.
HSTOP
C16
5V Tol, CMOS, BiDir PCI cycle stop signal. HSTOP is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. HSTOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
HDEVSEL
D15
5V Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device. As a
PCI initiator on the bus, the ISL3874 monitors HDEVSEL until a target responds. If no target
responds before timeout occurs, the ISL3874 terminates the cycle with an initiator abort.
HPERR
D16
5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the
HD31-HAD0 and BE3-BE0 buses. As an initiator during PCI cycles, the ISL3874 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared
to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
HGNT
C7
5V Tol, CMOS, ST
Input
PCI bus grant. HGNT is driven by the PCI bus arbiter to grant the ISL3874 access to the PCI bus
after the current data transaction has completed. HGNT may or may not follow a PCI bus request,
depending on the PCI bus parking algorithm.
HPCLK
A7
5V Tol, CMOS,
Input
HPCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
HPAR
B13
5V Tol, CMOS, BiDir PCI bus parity.
HIDSEL
C11
5V Tol, CMOS,
Input
Initialization device select. HIDSEL selects the ISL3874 during configuration space accesses.
HIDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
HPME
B8
CMOS, Output
Power Management Event Output. HPME provides output for PME signals.
TABLE 1. HOST INTERFACE PINS (Continued)
PIN NAME
PIN
NUMBER
PIN I/O TYPE
DESCRIPTION
ISL3874


Podobny numer części - ISL3874IK96

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Intersil Corporation
ISL3871A INTERSIL-ISL3871A Datasheet
37Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871IK18 INTERSIL-ISL3871IK18 Datasheet
28Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871IK18-TK INTERSIL-ISL3871IK18-TK Datasheet
28Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871IN18 INTERSIL-ISL3871IN18 Datasheet
28Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871IN18-TS INTERSIL-ISL3871IN18-TS Datasheet
28Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
More results

Podobny opis - ISL3874IK96

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Intersil Corporation
ISL3873 INTERSIL-ISL3873 Datasheet
215Kb / 31P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871A INTERSIL-ISL3871A Datasheet
37Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3880 INTERSIL-ISL3880 Datasheet
113Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3873A INTERSIL-ISL3873A Datasheet
778Kb / 42P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3871IK18 INTERSIL-ISL3871IK18 Datasheet
28Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
ISL3886 INTERSIL-ISL3886 Datasheet
43Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
logo
International Rectifier
ISL3893 IRF-ISL3893 Datasheet
108Kb / 1P
   Wireless LAN Integrated Medium Access Controller with Baseband Processor
logo
Intersil Corporation
HFA3841 INTERSIL-HFA3841 Datasheet
211Kb / 27P
   Wireless LAN Medium Access Controller
January 2000
HFA3842 INTERSIL-HFA3842 Datasheet
512Kb / 26P
   Wireless LAN Medium Access Controller
logo
OKI electronic componet...
MSM7712 OKI-MSM7712 Datasheet
157Kb / 20P
   Wireless LAN Baseband Controller
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com