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JN5189 Arkusz danych(PDF) 64 Page - NXP Semiconductors |
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JN5189 Arkusz danych(HTML) 64 Page - NXP Semiconductors |
64 / 92 page JN5189 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1.2 — June 2020 64 of 92 NXP Semiconductors IEEE 802.15.4 low power wireless MCU JN5189(T)/JN5188(T) 14.7 SPIFI timing Fig 15. USART interface timings Un_SCLK (CLKPOL = 0) TXD RXD Tcy(clk) tsu(D) th(D) tv(Q) START BIT0 tvQ) Un_SCLK (CLKPOL = 1) START BIT0 BIT1 BIT1 Table 34. SPIFI timing VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; EHS=1 for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge; simulated values. Symbol Parameter Min Typ Max Unit tcy(clk) Clock cycle time 30.0 ns tDS Data set-up time 3 ns tDH Data hold time 3 ns tV(Q) Data output valid time 5ns tH(Q) Data output hold time -10.5 ns Duty cycle 40 60 % tSS SSEL set-up time, time SSEL is low before first SCK edge 0.5 SCK cycles tSH SSEL hold time, time SSEL is low after last SCK 0.5 SCK cycles |
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