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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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IMX8MNIEC Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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IMX8MNIEC Arkusz danych(HTML) 11 Page - NXP Semiconductors |
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11 / 89 page  Modules list i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020 NXP Semiconductors 11 SDMA Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine. It helps in maximizing system performance by offloading the various cores in dynamic data routing. It has the following features: • Powered by a 16-bit Instruction-Set micro-RISC engine • Multi channel DMA supporting up to 32 time-division multiplexed DMA channels • 48 events with total flexibility to trigger any combination of channels • Memory accesses including linear, FIFO, and 2D addressing • Shared peripherals between Arm and SDMA • Very fast Context-Switching with 2-level priority based preemptive multi tasking • DMA units with auto-flush and prefetch capability • Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) • DMA ports can handle unidirectional and bidirectional flows (Copy mode) • Up to 8-word buffer for configurable burst transfers for EMIv2.5 • Support of byte-swapping and CRC calculations • Library of Scripts and API is available SJC Secure JTAG Controller The SJC provides JTAG interface (designed to be compatible with JTAG TAP standards) to internal logic. The i.MX 8M Nano family of processors uses JTAG port for system debugging. The JTAG port must be accessible during platform initial laboratory bring-up, for troubleshooting, as well as for software debugging by authorized entities. The i.MX 8M Nano SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. SNVS Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control, and Violation/Tamper Detection and reporting. SPDIF1 Sony Philips Digital Interconnect Format A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. It supports Transmitter and Receiver functionality. TEMPSENSOR Temperature Sensor Temperature sensor TZASC Trust-Zone Address Space Controller The TZASC (TZC-380 by Arm) provides security address region control functions required for intended application. It is used on the path to the DRAM controller. UART1 UART2 UART3 UART4 UART Interface Each of the UARTv2 modules supports the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) • Programmable baud rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud Table 3. i.MX 8M Nano modules list (continued) Block mnemonic Block name Brief description |
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