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RM48L940 Arkusz danych(PDF) 84 Page - Texas Instruments |
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RM48L940 Arkusz danych(HTML) 84 Page - Texas Instruments |
84 / 174 page RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 www.ti.com 6.13 On-Chip SRAM Initialization and Testing 6.13.1 On-Chip SRAM Self-Test Using PBIST 6.13.1.1 Features • Extensive instruction set to support various memory test algorithms • ROM-based algorithms allow application to run TI production-level memory tests • Independent testing of all on-chip SRAM 6.13.1.2 PBIST RAM Groups Table 6-25. PBIST RAM Grouping TEST PATTERN (ALGORITHM) MARCH 13N(1) MARCH 13N(1) TRIPLE READ TRIPLE READ TWO PORT SINGLE PORT MEMORY RAM GROUP TEST CLOCK MEM TYPE SLOW READ FAST READ (CYCLES) (CYCLES) ALGO MASK ALGO MASK ALGO MASK ALGO MASK 0x1 0x2 0x4 0x8 PBIST_ROM 1 ROM CLK ROM 24578 8194 STC_ROM 2 ROM CLK ROM 19586 6530 DCAN1 3 VCLK Dual Port 25200 DCAN2 4 VCLK Dual Port 25200 DCAN3 5 VCLK Dual Port 25200 ESRAM1(2) 6 HCLK Single Port 266280 MIBSPI1 7 VCLK Dual Port 33440 MIBSPI3 8 VCLK Dual Port 33440 MIBSPI5 9 VCLK Dual Port 33440 VIM 10 VCLK Dual Port 12560 MIBADC1 11 VCLK Dual Port 4200 DMA 12 HCLK Dual Port 18960 N2HET1 13 VCLK Dual Port 31680 HTU1 14 VCLK Dual Port 6480 RTP 15 HCLK Dual Port 37800 MIBADC2 18 VCLK Dual Port 4200 N2HET2 19 VCLK Dual Port 31680 HTU2 20 VCLK Dual Port 6480 ESRAM5(3) 21 HCLK Single Port 266280 ESRAM6(4) 22 HCLK Single Port 266280 23 8700 Dual Port ETHERNET 24 VCLK3 6360 25 Single Port 133160 ESRAM8(5) 28 HCLK Single Port 266280 (1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing. (2) ESRAM1: Address 0x08000000 - 0x0800FFFF (Always on power domain) (3) ESRAM5: Address 0x08010000 - 0x0801FFFF (RAM power domain 1) (4) ESRAM6: Address 0x08020000 - 0x0802FFFF (RAM power domain 2) (5) ESRAM8: Address 0x08030000 - 0x0803FFFF (RAM power domain 3) Not available on theRM48L540 device. The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100 MHz. The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58. 84 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
Podobny numer części - RM48L940_V01 |
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Podobny opis - RM48L940_V01 |
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