8 Detailed Description

8.1 Overview

The SN74HCS16507-Q1 is a parallel- or serial-in, serial-out 8-bit shift register with Schmitt-trigger inputs and

open-drain outputs.

This device has two modes of operation: load data, and shift data.

When the shift or load (SH/LD) input is held in the low state, the internal registers are loaded with data from the

eight lettered inputs (A-H). This operation is asynchronous. In this state, the output (Q) will have the same state

as the input H, while the inverted output (Q) will have the opposite state.

When the shift or load (SH/LD) input is held in the high state, the internal registers hold their current state until a

clock pulse is received. On the rising edge of the clock (CLK) input, data from the serial input will be loaded into

the first register, and the data in the internal registers will be shifted by one place. The last register will lose its

value. The output (Q) will always be in the same state as the last register, and the inverted output (Q) will have

the opposite state. The clock inhibit (CLK INH) input can be held high to prevent clock pulses from being

detected. CLK and CLK INH are interchangable inputs.

8.2 Functional Block Diagram

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS16507-Q1

SH/LD

SER

CLK INH

CLK

A

D

S

R

Q

B

D

S

R

Q

5 Additional

Shift Register

Stages

C

D

E

F

G

H

D

S

R

Q

Q

8.3 Feature Description

8.3.1 Open-Drain CMOS Outputs

This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the

high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may

create fast edges into light loads so routing and load conditions should be considered to prevent ringing.

Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without

being damaged. It is important for the output power of the device to be limited to avoid damage due to

overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all

times.

When placed into the high-impedance state, the output will neither source nor sink current, with the exception of

minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output

voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to

the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected

to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the

SN74HCS16507-Q1

SCLS824 – AUGUST 2020

www.ti.com

10

Submit Document Feedback

Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: SN74HCS16507-Q1