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TLV3604 Arkusz danych(PDF) 9 Page - Texas Instruments |
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TLV3604 Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 17 page 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TLV360x comparators feature rail-to-rail inputs and outputs on supply voltages as low as 2.4 V. The LVDS output stage is optimal for high speed applications that require low power consumption. The 850 ps propagation delay of the device makes it a suitable fit for applications involving optical reception, triggers for test and measurement systems, and transceiver type applications that require a high speed signal to be carried over a certain distance. 8.1.1 Comparator Inputs The TLV360x is a rail-to-rail input comparator, with an input common-mode range that exceeds the supply rails by 200 mV for both positive and negative supplies. 8.1.2 Capacitive Loads Under reasonable capacitive loads, the device maintains specified propagation delay. However, excessive capacitive loading under high switching frequencies may increase supply current, propagation delay, or induce decreased slew rate. 8.1.3 Latch Functionality The latch pin of the TLV3605 holds the output state of the device when the LE/HYST pin is less than 800mV above VEE. Figure 8-1, Figure 8-2 and Figure 8-3 illustrate proper latch timing for the device. Latch hold time is defined as the amount of time after the latch pin is asserted in which the input signal must remain stable (not force output toggle) in order to hold the proper output state at the time the latch pin was asserted. Latch setup time is the amount of time the input should be stable before the latch pin is asserted low. Figure 8-1 illustrates the amount of setup time needed for the output to properly latch an input state change. Figure 8-2 shows a proper amount of setup and hold time for a short input pulse when the latch pin is asserted such that the output latches the correct state. Figure 8-3 shows the timing diagram for when the latch pin is asserted high, and the time it takes for the output to properly unlatch. LE/HYS t > tsetup IN OUT Figure 8-1. Input Change Properly Latched www.ti.com TLV3604 SNOSDA2A – AUGUST 2020 – REVISED AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV3604 |
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