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TSB42AA9I Arkusz danych(PDF) 9 Page - Texas Instruments

Numer części TSB42AA9I
Szczegółowy opis  STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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1–3
1.5
Terminal Descriptions
The terminal descriptions in this section are grouped by functionality with the package pin numbers added for
reference. The following conventions are used in the tables: signals with overbar denote an active low signal; (I)
denotes an input; (O) denotes an output; (I/O) denotes a 3-state input and output.
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
POWER
GND
5, 21, 35, 50,
57, 71, 84, 90,
94
I
Device ground terminals
VDD
2, 10, 29, 32,
41, 54, 62, 76,
80, 86
I
3.3V power supply terminals
REG18_1,
REG18_2
33, 81
O
Regulates the 3.3 V supply for core 1.8 V. These pins should be tied to GND through 0.1
µF decoupling
capacitors.
EN
22
I
Enable for 1.8 V regulators (active low). This pin should be tied to GND during normal operation.
RESET
31
I
Power-on reset input (active low).
ATA/ATAPI INTERFACE
DD[15:0]
48, 51, 53, 56,
59, 61, 64, 66,
67, 65, 63, 60,
58, 55, 52, 49
I/O
Host-device data bus. This is an 8- or 16-bit bidirectional data interface between the host and the storage
device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16-bits wide. DD15 is the
most significant bit.
DA[2:0]
38, 40, 39
O
Device address 0 to 2. This is the 3-bit binary coded address asserted by the host to access a register or
data port in the storage device.
CS0
37
O
Chip select 0 (active low). This chip select signal is used by the host to select the command block
registers in the ATA controller in the storage device.
CS1
36
O
Chip select 1 (active low). This chip select signal is used by the host to select the command block
registers in the ATA controller.
INTRQ
42
I
Interrupt request. This signal is used by the ATA controller in the storage device to interrupt its host
system. INTRQ is asserted only when the controller has a pending interrupt.
DMACK
43
O
DMA acknowledge (active low). This signal from the host handshakes with the DMARQ for the DMA
transfers.
DMARQ
47
I
DMA request. This signal, used for DMA data transfers between host and storage device, is asserted by
the ATA controller in the device when it is ready to transfer data to or from the host. This signal is released
(high impedance state) whenever the device is not selected or is selected and no DMA command is in
progress.
IORDY
(DDMARDY,
DSTROBE)
44
I
I/O ready. This signal is negated to extend the transfer cycle of any host ATA register access (read or
write) when the ATA controller is not ready to respond to a data transfer request. The use of IORDY is
required for PIO modes 3 and above, and otherwise is optional.
(Ultra DMA ready (active low). This signal is a flow control for Ultra DMA data out bursts. It is asserted by
the ATA device to indicate to the host that the device is ready to receive Ultra DMA data out bursts.
Ultra DMA data strobe. This signal is the data in strobe from the device for an Ultra DMA data in burst.)
DIOR
(HDMARDY,
HSTROBE)
45
O
Read strobe signal (active low). The falling edge of DIOR enables data from the ATA device onto the
signals, DD (7:0) or DD (15:0). The rising edge of DIOR latches data into the device. The device does not
act on the data until it is latched. The direction of data (16 bits) transfer is controlled by DIOR and DIOW.
(Ultra DMA ready (active low). This is a flow control signal for ultra DMA in bursts. It is asserted by the
host to indicate to the device that the host is ready to receive ultra DMA data in bursts.
Ultra DMA data strobe. This is the data out strobe from the host for an ultra DMA data out burst.)
DIOW
(STOP)
46
O
Write strobe signal (active low). The rising edge of DIOW latches data from the signals, DD (7:0) or DD
(15:0), into the ATA device. The ATA device does not act on the data until it is latched. The direction of
data (16 bits) transfer is controlled by DIOR and DIOW.
(Stop ultra DMA burst. This signal is negated by the host prior to initiation of an ultra DMA burst.)
RSTATCTL
68
O
Reset ATA controller (active low). This output allows the host to asynchronously reset the ATA controller
of the device.


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