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FIN12ACGFX Arkusz danych(PDF) 4 Page - Fairchild Semiconductor |
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FIN12ACGFX Arkusz danych(HTML) 4 Page - Fairchild Semiconductor |
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4 / 21 page  Preliminary www.fairchildsemi.com 4 Power-Down Mode Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state the PLL and references will be disabled, differ- ential input buffers will be shut off, differential output buffers will be placed into a HIGH Impedance state, LVCMOS out- puts will be placed into a HIGH Impedance state, and LVC- MOS inputs will be driven to a valid level internally. Additionally all internal circuitry will be reset. The loss of CKREF state is also enabled to insure that the PLL will only power-up if there is a valid CKREF signal. In a typical application mode signals of the device will not change other than between the desired frequency range and the power-down mode. This allows for system level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a “logic 0” should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a “logic 1” should be con- nected to a system level power-down signal. Serializer Operation Mode The serializer configurations are described in the following sections. The basic serialization circuitry works essentially identical in these modes but the actual data and clock streams will differ dependent on if CKREF is the same as the STROBE signal or not. When it is stated that CKREF STROBE this means that the CKREF and STROBE signals have an identical frequency of operation but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE then each signal is distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower fre- quency than STROBE. Serializer Operation: (Figure ) Modes 1, 2, or 3 DIRI equals 1 CKREF equals STROBE The PLL must receive a stable CKREF signal in order to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked the device can begin to capture and serialize data. Data will be captured on the ris- ing edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode the internal deseri- alizer circuitry is disabled including the DS input buffer. The CKSI serial inputs remain active to allow the pass through of the CKSI signal to the CKP output. For more on this mode please see the section on Passing a Word Clock. If this mode is not needed then the CKSI inputs can either be driven to valid levels or left to float. For lowest power oper- ation let the CKSI inputs float. Serializer Operation: (Figure ) DIRI equals 1 CKREF does not equal STOBE If the same signal is not used for CKREF and STROBE, then the CKREF signal must be run at a higher frequency than the STROBE rate in order to serialize the data cor- rectly. The actual serial transfer rate will remain at 14 times the CKREF frequency. A data value of zero will be sent when no valid data is present in the serial bit stream. The operation of the serializer will otherwise remain the same. The exact frequency that the reference clock needs to run at will be dependent upon the stability of the CKREF and STROBE signal. If the source of the CKREF signal imple- ments spread spectrum technology then the minimum fre- quency of this spread spectrum clock should be used in calculating the ratio of STROBE frequency to the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-cycle variation then the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency. Serializer Operation: (Figure ) DIRI equals 1 No CKREF A third method of serialization can be done by providing a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. At power-up the device is configured to accept a serializa- tion clock from CKSI. If a CKREF is received then this device will enable the CKREF serialization mode. The device will remain in this mode even if CKREF is stopped. To re-enable this mode the device must be powered down and then powered back up with “logic 0” on CKREF. |
Podobny numer części - FIN12ACGFX |
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Podobny opis - FIN12ACGFX |
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