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LD3986J3133R-E Arkusz danych(PDF) 3 Page - STMicroelectronics |
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3 / 12 page LD3986 SERIES 3/12 Figure 2: Pin Connection (top through view) Table 4: Pin Description Figure 3: Typical Application Circuit Symbol Pin N° Name and Function VO2 A1 Output Voltage 2 of the dual LDO EN2 B1 Enables voltage for output voltage 2: ON MODE when VEN ≥ 1.4V, OFF MODE when VEN ≤ 0.4V (Do not leave floating, not internally pulled down/up) BYPASS C1 Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise voltage GND C2 Common Ground GND C3 Common Ground EN1 B3 Enables voltage for output voltage 1: ON MODE when VEN ≥ 1.4V, OFF MODE when VEN ≤ 0.4V (Do not leave floating, not internally pulled down/up) VO1 A3 Output Voltage 1 of the dual LDO VI A2 Input Voltage for both LDO |
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