GS8170LW36/72C-333/300/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 2.03 1/2005

7/27

© 2002, GSI Technology, Inc.

Special Functions

Burst Cycles

SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.

The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter

generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM

by driving the ADV pin low, into Load mode.

SigmaRAM Pipelined Burst Reads with Counter Wraparound

SigmaRAM Late Write SRAM Burst Writes with Counter Wraparound

Read A

Cont A+1

Cont A+2

Cont A+3

Cont A

Deselect

A

Q(A)

Q(A+1)

Q(A+2)

Q(A+3)

Q(A)

CK

Address

ADV

E1

W

DQA0–DQA8

CQ

Write A+2

Cont A+3

Cont A

Cont A+1

Cont A+2

Deselect

A+2

D(A+2)

D(A+3)

D(A)

D(A+1)

D(A+2)

CK

Address

ADV

E1

W

Ba–Bb

DQ

CQ