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AD9445BSVZ-125 Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD9445BSVZ-125
Szczegółowy opis  14-Bit, 105/125 MSPS, IF Sampling ADC
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9445BSVZ-125 Arkusz danych(HTML) 6 Page - Analog Devices

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AD9445
Rev. 0 | Page 6 of 40
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Full
2.0
2.0
V
Low Level Input Voltage
Full
0.8
0.8
V
High Level Input Current
Full
200
200
μA
Low Level Input Current
Full
−10
+10
−10
+10
μA
Input Capacitance
Full
2
2
pF
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Full
3.25
3.25
V
Low Level Output Voltage
Full
0.2
0.2
V
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)
VOD Differential Output Voltage2
Full
247
545
247
545
mV
VOS Output Offset Voltage
Full
1.125
1.375
1.125
1.375
V
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Full
0.2
0.2
V
Common-Mode Voltage
Full
1.3
1.5
1.6
1.3
1.5
1.6
V
Differential Input Resistance
Full
1.1
1.4
1.7
1.1
1.4
1.7
Differential Input Capacitance
Full
2
2
pF
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
105
125
MSPS
Minimum Conversion Rate
Full
10
10
MSPS
CLK Period
Full
9.5
8.0
ns
CLK Pulse Width High1 (tCLKH)
Full
3.8
3.2
ns
CLK Pulse Width Low1 (tCLKL)
Full
3.8
3.2
ns
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Full
3.35
3.35
ns
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Full
2.1
3.6
4.8
2.3
3.6
4.8
ns
Pipeline Delay (Latency)
Full
13
13
Cycles
Aperture Delay (tA)
Full
ns
Aperture Uncertainty (Jitter, tJ)
Full
60
60
fsec
rms
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.


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