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ADC1242CIJ Arkusz danych(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC1242CIJ
Szczegółowy opis  12-Bit Plus Sign Sampling A/D Converter
Download  14 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC1242CIJ Arkusz danych(HTML) 4 Page - National Semiconductor (TI)

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AC Electrical Characteristics
The following specifications apply for DVCC e AVCC ea50V Vb eb50V tr e tf e 20 ns unless otherwise specified
Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7)
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 9)
(Notes 10 18)
(Limits)
fCLK
Clock Frequency
20
MHz
05
MHz(min)
40
MHz(max)
Clock Duty Cycle
50
%
40
%(min)
60
%(max)
tC
Conversion Time
27(1fCLK)
27(1fCLK) a 300 ns
(max)
fCLKe 20 MHz
135
m
s
tA
Acquisition Time
RSOURCE e 50X
7(1fCLK)
7(1fCLK) a 300 ns
(max)
(Note 15)
fCLK e 20 MHz
35
m
s
tZ
Auto Zero Time
26
26
1fCLK(max)
fCLK e 20 MHz
13
m
s
tCAL
Calibration Time
1396
1fCLK
fCLK e 20 MHz
698
706
m
s(max)
tW(CAL)L
Calibration Pulse Width
(Note 16)
60
200
ns(min)
tW(WR)L
Minimum WR Pulse Width
60
200
ns(min)
tACC
Maximum Access Time
CL e 100 pF
(Delay from Falling Edge of
50
85
ns(max)
RD to Output Data Valid)
t0H t1H
TRI-STATE Control (Delay
RL e 1kX
from Rising Edge of RD
CL e 100 pF
30
90
ns(max)
to Hi-Z State)
tPD(INT)
Maximum Delay from Falling Edge of
100
175
ns(max)
RD or WR to Reset of INT
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC) the current at that pin should be limited to
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature) iJA (package
junction to ambient thermal resistance) and TA (ambient temperature) The maximum allowable power dissipation at any temperature is PDmax e (TJmax b
TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this device TJmax e 125 C and the typical thermal resistance (iJA)ofthe
ADC1242 CIJ when board mounted is 47 CW
Note 5
Human body model 100 pF discharged through a 15 kX resistor
Note 6
Two on-chip diodes are tied to the analog input as shown below Errors in the AD conversion can occur if these diodes are forward biased more than
50 mV
TLH11735 – 3
This means that if AVCC and DVCC are minimum (475 VDC) and V
b
is maximum (b475 VDC) full-scale must be s 48 VDC
4


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