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AD1836A Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD1836A
Szczegółowy opis  Multichannel 96 kHz Codec
Download  24 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD1836A Arkusz danych(HTML) 6 Page - Analog Devices

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AD1836A
Table 7. Timing Specifications
Parameter
Comments
Min
Max
Unit
tMH
MCLK High
512 × fS Mode
18
ns
tML
MCLK Low
512 × fS Mode
18
ns
tMCLK
MCLK Period
512 × fS Mode
36
ns
fMCLK
MCLK Frequency
512 × fS Mode
27
MHz
tPDR
PD/RST Low
5
ns
MASTER CLOCK AND RESET
tPDRR
PD/RST Recovery
Reset to Active Output
4500
tMCLK
tCHH
CCLK High
10
ns
tCHL
CCLK Low
10
ns
tCDS
CDATA Setup
To CCLK Rising
5
ns
tCDH
CDATA Hold
From CCLK Rising
5
ns
tCLS
CLATCH Setup
To CCLK Rising
5
ns
tCLH
CLATCH Hold
From CCLK Falling
5
ns
tCODE
COUT Enable
From CCLK Falling
10
ns
tCOD
COUT Delay
From CCLK Falling
10
ns
tCOH
COUT Hold
From CCLK Falling
0
ns
SPI PORT
tCOTS
COUT Three-State
From CCLK Falling
10
ns
tDBH
DBCLK High
15
ns
tDBL
DBCLK Low
15
ns
fDB
DBCLK Frequency
64 × fS
ns
tDLS
DLRCLK Setup
To DBCLK Rising
0
ns
tDLH
DLRCLK Hold
From DBCLK Rising
10
ns
tDDS
DSDATA Setup
To DBCLK Rising
0
ns
DAC SERIAL PORT
(Normal Modes)
tDDH
DSDATA Hold
From DBCLK Rising
20
ns
tDBH
DBCLK High
15
ns
tDBL
DBCLK Low
15
ns
fDB
DBCLK Frequency
256 × fS
ns
tDLS
DLRCLK Setup
To DBCLK Rising
0
ns
tDLH
DLRCLK Hold
From DBCLK Rising
10
ns
tDDS
DSDATA Setup
To DBCLK Rising
0
ns
DAC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
tDDH
DSDATA Hold
From DBCLK Rising
20
ns
tABD
ABCLK Delay
15
ns
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
tALS
LRCLK Skew
From ABCLK Falling
–2
+2
ns
ADC SERIAL PORT
(Normal Modes)
tABDD
ASDATA Delay
From ABCLK Falling
5
ns
tABD
ABCLK Delay
15
ns
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
tALS
LRCLK Skew
From ABCLK Falling
–2
+2
ns
ADC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
tABDD
ASDATA Delay
From ABCLK Falling
5
ns
tABD
ABCLK Delay
15
ns
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
tALS
LRCLK Skew
From ABCLK Falling
–2
+2
ns
tABDD
ASDATA Delay
From ABCLK Falling
5
ns
tDDS
DSDATA1 Hold
To ABCLK Rising
0
ns
ADC SERIAL PORT
(TDM Packed AUX)
tDDH
DSDATA1 Hold
From ABCLK Rising
7
ns
tAXDS
AAUXDATA Setup
To AUXBCLK Rising
7
ns
tAXDH
AAUXDATA Hold
From AUXBCLK Rising
10
ns
AUXILIARY INTERFACE
tDXDD
DAUXDATA Delay
From AUXBCLK Falling
25
ns
Rev. 0 | Page 6 of 24


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